NEC PD78212, Руководство пользователя

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170
µ
PD78214 Sub-Series
(c) Restart before 0 is set in TM2 cleared
Count clock
TM2
CE2
n-1
When the CE2 bit is set to 1 before this count clock, Clearing
TM2 by CE2
←
0 and counting by CE2
←
1 are performed simultaneously.
n 0 1 2
7.3.5 External Event Counter Function
Eight-bit timer/counter 2 can count clock pulses externally applied to the CI pin.
The external event counter operation mode requires no particular selection method. TM2 functions as an external
event counter when external count input is specified for the count clock of TM2 by setting the higher 4 bits of
prescaler mode register 1 (PRM1).
The maximum frequency of an external clock pulse that can be counted by TM2 functioning as an external event
counter is 187.5 kHz when occurrences of both CI input signal edges are counted, and is 250 kHz when occurrences
of only one edge are counted (f
CLK
= 6 MHz).
When occurrences of both edges are counted, the external clock pulse signal must have a pulse width of 16 system
clock pulses (2.67
µ
s: f
CLK
= 6 MHz) or more for both the high level and the low level. If the pulse width is less than
this value, no edges may be counted. When occurrences of only one edge are counted, the external clock pulse
signal must have a pulse width of 12 system clock pulses (2
µ
s: f
CLK
= 6 MHz) or more for both the high level and
the low level. If the pulse width is less than this value, no edges may be counted.
Fig. 7-75 shows the external event count timing of 8-bit timer/counter 2.