National Semiconductor COP820CJ, Руководство пользователя

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COP820CJ
/COP
822
CJ/C
OP8
23C
J
Pin D e s c rip tio n
(Continued)
Pins G1 and G2 currently do not have any alternate func­
tions.
The selection of alternate Port G functions are done through
registers PSW [OOEF] to enable external interrupt and
CNTRL1 [OOEE] to select TIO and MICROWIRE operations.
PORT D is a four bit output port that is preset when RESET
goes low. One data memory address location is allocated
for the data register [OODC].
Note: Care must be exercised with the D2 pin operation. At RESET, the
external loads on this pin must ensure that the output voltages stay above
0.8 Vcc t0 prevent the chip from entering special modes. Also keep the
external loading on D2 to less than 1000 pF.
F u n c tio n a l D e s c rip tio n
The internal architecture is shown in the block diagram.
Data paths are illustrated in simplified form to depict how
the various logic elements communicate with each other in
implementing the instruction set of the device.
ALU and CPU Registers
The ALU can do an 8-bit addition, subtraction, logical or
shift operations in one cycle time. There are five CPU regis­
ters:
A is the 8-bit Accumulator register
PC is the 15-bit Program Counter register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is the 8-bit address register and can be auto incre­
mented or decremented.
X is the 8-bit alternate address register and can be auto
incremented or decremented.
SP is the 8-bit stack pointer which points to the subrou­
tine stack (in RAM).
B, X and SP registers are mapped into the on chip RAM.
The B and X registers are used to address the on chip RAM.
The SP register is used to address the stack in RAM during
subroutine calls and returns. The SP must be preset by soft­
ware upon initialization.
M e m o ry
The memory is separated into two memory spaces: program
and data.
PROGRAM MEMORY
Program memory consists of 1024 x 8 ROM. These bytes of
ROM may be instructions or constant data. The memory is
addressed by the 15-bit program counter (PC). ROM can be
indirectly read by the LAID instruction for table lookup.
DATA MEMORY
The data memory address space includes on chip RAM, I/O
and registers. Data memory is addressed directly by the in­
struction or indirectly through B, X and SP registers. The
device has 64 bytes of RAM. Sixteen bytes of RAM are
mapped as “ registers” , these can be loaded immediately,
decremented and tested. Three specific registers: X, B, and
SP are mapped into this space, the other registers are avail­
able for general usage.
Any bit of data memory can be directly set, reset or tested.
All I/O and registers (except A and PC) are memory
mapped; therefore, I/O bits and register bits can be directly
and individually set, reset and tested, except the write once
only bit (WDREN, WATCHDOG Reset Enable), and the un­
used and read only bits in CNTRL2 and WDREG registers.
Note: RAM contents are undefined upon power-up.
R e s e t
EXTERNAL RESET
The RESET input pin when pulled low initializes the micro­
controller. The user must insure that the RESET pin is held
low until Vcc is within the specified voltage range and the
clock is stabilized. An R/C circuit with a delay 5x greater
than the power supply rise time is recommended
(Figure 4).
The device immediately goes into reset state when the
RESET input goes low. When the RESET pin goes high the
device comes out of reset state synchronously. The device
will be running within two instruction cycles of the RESET
pin going high. The following actions occur upon reset:
Port L TRI-STATE
Port G TRI-STATE
Port D HIGH
PC CLEARED
RAM Contents RANDOM with Power-On-
Reset
UNAFFECTED with external
Reset (power already applied)
B, X, SP Same as RAM
PSW, CNTRL1, CNTRL2
and WDREG Reg. CLEARED
Multi-Input Wakeup Reg.
WKEDG, WKEN
CLEARED
WKPND UNKNOWN
Data and Configuration
Registers for L & G
CLEARED
WATCHDOG Timer Prescaler/Counter each
loaded with FF
The device comes out of the HALT mode when the RESET
pin is pulled low. In this case, the user has to ensure that the
RESET signal is low long enough to allow the oscillator to
restart. An internal 256 tc delay is normally used in conjunc­
tion with the two pin crystal oscillator. When the device
comes out of the HALT mode through Multi-Input Wakeup,
this delay allows the oscillator to stabilize.
The following additional actions occur after the device
comes out of the HALT mode through the RESET pin.
If a two pin crystal/resonator oscillator is being used:
RAM Contents UNCHANGED
Timer T1 and A Contents UNKNOWN
WATCHDOG Timer Prescaler/Counter ALTERED
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