National Semiconductor COP820CJ, Руководство пользователя

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COP820CJ
/COP
822
CJ/C
OP8
23C
J
In s tru c tio n S e t
REGISTER AND SYMBOL DEFINITIONS Symbols
Reaisters
[B] Memory indirectly addressed by B register
A 8-bit Accumulator register
B 8-bit Address register
X 8-bit Address register
SP 8-bit Stack pointer register
PC 15-bit Program counter register
PU upper 7 bits of PC
PL lower 8 bits of PC
C 1-bit of PSW register for carry
HC Half Carry
GIE 1-bit of PSW register for global interrupt enable
[X] Memory indirectly addressed by X register
Mem Direct address memory or [B]
Mem! Direct address memory or [B] or Immediate data
Imm
8-bit Immediate data
Reg Register memory: addresses FO to FF (Includes B, X
and SP)
Bit Bit number (0 to 7)
<— Loaded with
< — > Exchanged with
Instruction Set
ADD add A 4— A + Meml
ADC add with carry A <— A + Meml + C, C <— Carry
HC <— Half Carry
SUBC subtract with carry A * — A + Meml +C, C «— Carry
HC x - Half Carry
AND Logical AND A <— A and Meml
OR Logical OR A <— A or Meml
XOR Logical Exclusive-OR
A <— AxorMeml
IFEQ IF equal Compare A and Meml, Do next if A = Meml
IFGT IF greater than Compare A and Meml, Do next if A > Meml
IFBNE
IF B not equal
Do next if lower 4 bits of B ¥= Imm
DRSZ
Decrement Reg. .skip if zero
Reg * — Reg - 1, skip if Reg goes to 0
SBIT
Set bit
1 to bit,
Mem (bit = 0 to 7 immediate)
RBIT Reset bit 0 to bit,
Mem
IFBIT If bit If bit,
Mem is true, do next instr.
X Exchange A with memory
A < — > Mem
LD A Load A with memory
A 4— Meml
LD mem
Load Direct memory Immed.
Mem 4— Imm
LDReg Load Register memory Immed. Reg <— Imm
X Exchange A with memory [B] A «—► [B] (B < - B ±1)
X Exchange A with memory [X] A ► [X] (X <— X + 1)
LD A Load A with memory [B] A [B] (B < - B±1)
LD A Load A with memory [X]
A < - [X] (X < - X ±1)
LD M Load Memory Immediate [B] < - Imm (B < - B ±1)
CLRA Clear A A * — 0
INCA Increment A A «— A + 1
DECA Decrement A A <— A - 1
LAID Load A indirect from ROM
A 4 - ROM(PU.A)
DCORA DECIMAL CORRECT A A <— BCD correction (follows ADC, SUBC)
RRCA ROTATE A RIGHT THRU C C —* A7 AO —► C
SWAPA Swap nibbles of A A 7 . . . A4 «— > A 3 ... AO
SC SetC C 1,HC « - 1
RC Reset C C 0, HC •«— 0
IFC IfC If C is true, do next instruction
IFNC If not C If C is not true, do next instruction
JMPL Jump absolute long PC «— ii (ii = 15 bits, 0 to 32k)
JMP Jump absolute PC11..Q * - i(i = 12 bits)
JP Jump relative short . PC ■*— PC + r (r is -3 1 to +32, not 1)
JSRL Jump subroutine long [SP] 4 - PL,[SP-1 ] 4 - PU.SP-2.PC 4 - ii
JSR Jump subroutine [SP] 4r- PL,[SP-1] 4 - PU,SP-2,PC11..0 « - i
JID Jump indirect PL < - ROM(PU,A)
RET Return from subroutine SP + 2.PL [SP],PU [SP-1]
RETSK Return and Skip SP + 2.PL 4— [SPj.PU 4— [SP-1],Skip next instruction
RETI Return from Interrupt SP + 2.PL 4 - [SP],PU 4 - [SP-1],GIE 4 - 1
INTR Generate an interrupt [SP] 4 - PL,[SP-1] 4 - PU,SP-2,PC 4 - OFF
NOP No operation PC 4 r- PC + 1
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