National Semiconductor COP820CJ, Руководство пользователя

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M o d u la to r /T im e r
(Continued)
START/STOP
T L /D D /1 1 2 0 8 -1 7
256 ^ (MAX.)
FIGURE 14. Mode 2a: 50% Duty Cycle Output
T L /D D /1 1 2 0 8 -1 8
MODRL
REGISTER
r 4 .
INTERNAL DATA BUS
-------------- : k
i k
7 6
5 ,
f
0
AUTO RELOAD MC3
MC2 MC1
|
8- BIT =0 = 1
R Q S
I
I LK
8-BIT
START/STOP
1
"IIDERTLCV:
CNTRL2
REGISTER
TIMER Tt
UNDERFLOW
L7 PIN
T L /D D /1 1 2 0 8 -1 9
UNDERFLOW I I UNDERFLOW
—
u }
—
256 (MAX.)
CONTROLLED BY T1
FIGURE 15. Mode 2b: Variable Duty Cycle Output
T L /D D /1 1208-20
1-65
COP82
0CJ
/COP
822
CJ/C
OP8
23C
J