National Semiconductor ADS42B4 Series, Руководство пользователя

Страница: 5 / 17

ADS42B49EVM TSW1400
L
VD
S
CLK
+5V
Mini-USB
PC
Signal
Generator
+5V
Mini-USB
J17
J23
J19
J3/J6
J5
J12
J4 J8
RX IF
BPF
Signal
Generator
±
1dBFS
15dBm
Ref_out
Ref_in
www.ti.com
Basic Test Procedure
2.1 Test Block Diagram
The test set-up for general testing of the ADS42B4x EVM with the TSW1400 capture card is shown in
Figure 3 .
Figure 3. Test Set-Up Block Diagram
2.2 Verify Board Set-up
Verify jumper settings are in the correct position as outlined in Table 1 and Table 2 . Parallel configuration
is not recommended because the high performance modes cannot be enabled. The high performance
modes are required to achieve best performance.
Table 1. Default ADS42Bxx EVM Revision A Jumper Setting for Serial Interface
Jumper Default position Function
JP15 Short 1 - 2 DC supply for +1.8VA
JP16 Short 1 - 2 DC supply for +1.8VD
JP17 Short 3 - 2 DC supply, LDO for +5V
JP19 Short 3 - 2 DC supply, LDO for +1.8V
JP28 Short 3 - 2 DC supply, LDO for +5V
JP29 Short 3 - 2 DC supply, LDO for +3.3VCLK
JP26 Open DC supply for ext buffer
JP27 Open DC supply for ext buffer
JP3 Short 2 - 3 OPA power down
JP4 Short 2 - 3 OPA power down
JP22 Open SDOUT to FPGA
JP20 Short 1 - 2 CDC
JP21 Short 1 - 2 CDC
J14 Short 1 - 2 CDC power down
J18 Open CDC, VCXO
JP8
(1)
Short 3 - 2 ADC SCLK for SPI
JP9 Short 3 - 2 ADC SDATA for SPI
JP10 Short 3 - 2 ADC SEN for SPI
JP11 Short 3 - 2 ADC for SPI, also reset
JP 12 Short 1 - 2 ADC Low speed mode disable
JP 13 Open
(1)
The EVM schematic shows default setting of JP8 to JP11 as parallel interface Table 2 ) which is for EVM installation. After EVM
tested and released these jumpers are set as serial interface ( Table 1 ).
5 SLAU477A – December 2012 – Revised January 2015 ADS42B4x EVM
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated