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PXIe-4330/4331 Calibration Procedure
Input Offset Verification
This section provides instructions for verifying the PXIe-4330/4331 input offset specifications.
Table 8 shows all settings for the PXIe-4330/4331. Throughout the input offset verification, use
Tables 24 and 25 to determine if the module is operating within its specified range.
Complete the following steps to test the input offset accuracy of the module.
1.
Configure the switch modules to connect to the channel you want to verify. Refer to Table 4
for the specific switch column and row configuration. The connection paths are shown in
Figure 13 in
Appendix A: Connection Path Details
.
2.
Create a DAQmx task.
3.
Create and configure an AI Bridge (V/V) channel.
4.
Configure the properties for the acquisition as described in Table 8.
5.
Start the task.
6.
Read 10,000 samples of data if
f
s
= 25600. Read 40,000 samples of data if
f
s
= 102400
7.
Average the readings that you acquired and record the result.
8.
Clear the task.
9.
Compare the final result to the
Upper Limit
and
Lower Limit
values in Table 24 for
f
s
≤
51.2 kHz and Table 25 for
f
s
> 51.2 kHz. If the result is between these values, the module
passes the test.
Table 4.
Offset Verify Switch Settings
Channel
S
witch 1
S
witch 2
0
r2->c4,r2->c11,r3->c12,
r3->c16
r0->c4,r1->c5,r0->c6,r1->c7,
r0->c14,r1->c16
1
r2->c4,r2->c11,r3->c12,
r3->c21
r0->c4,r1->c5,r0->c6,r1->c7,
r0->c19,r1->c21
2
r2->c4,r2->c11,r3->c12,
r3->c26
r0->c4,r1->c5,r0->c6,r1->c7,
r0->c24,r1->c26
3
r2->c4,r2->c11,r3->c12,
r3->c31
r0->c4,r1->c5,r0->c6,r1->c7,
r0->c29,r1->c31
4
r2->c4,r2->c11,r3->c12,
r3->c36
r0->c4,r1->c5,r0->c6,r1->c7,
r0->c34,r1->c36
5
r2->c4,r2->c11,r3->c12,
r3->c41
r0->c4,r1->c5,r0->c6,r1->c7,
r0->c39,r1->c41
6
r2->c4,r2->c11,r3->c12,
r3->c46
r0->c4,r1->c5,r0->c6,r1->c7,
r0->c44,r1->c46
0
r2->c4,r2->c11,r3->c12,
r3->c51
r0->c4,r1->c5,r0->c6,r1->c7,
r0->c49,r1->c51