National Instruments PCI-6528, Руководство пользователя

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Chapter 3 Programming
© National Instruments Corporation 3-3 Static DIO Register-Level Programmer Manual
If a device is found, the algorithm can store the configuration information of the device into
a data structure. Base Address Register 0 (BAR0) points to the base address of the PCI MITE,
while Base Address Register 1 (BAR1) points to the base address of the device registers. The
size of BAR0 is 4 KB, and the size of BAR1 is 8 KB.
Both addresses are most likely mapped above 1 MB in the memory map. This means that in
order to communicate with the device you must know how to perform memory cycles to
extended memory.
Tip To make communication with the device simpler, re-map the device below 1 MB in
the memory map using PCI BIOS read and write calls.
Example
This pseudocode example re-maps the device below 1 MB. If you choose not to re-map the
device, you can skip the first CWrite instruction, but you still need to perform the next and
last instructions to initialize the device. All values in this example are 32 bits.
Use the following pseudocode to re-map the PCI MITE to memory address 0xD0000 and the
device to memory address 0xD1000:
PCI-6528 0x70A9 24 Input, 24 Output, 60 V, Ch-Ch Isolated Digital I/O
PXI-6509 0x1710 96 Channel, 5 V, TTL/CMOS Digital I/O
PXI-6511 0x70D3 64 Sink/Source Input, 30 V, Bank-Isolated Digital Input
PXI-6512 0x70D2 64 Source Output, 30 V, Bank-Isolated Digital Output
PXI-6513 0x70D1 64 Sink Output, 30 V, Bank-Isolated Digital Output
PXI-6514 0x70CD 32 Source/Sink Input, 32 Source Output, 30 V, Bank-Isolated Digital I/O
PXI-6515 0x70C9 32 Input, 32 Sink Output, 30 V, Bank-Isolated Digital I/O
PXI-6521 0x718C 8 Output, 8 Input, 60 V, Ch-Ch Isolated Digital I/O
PXI-6528 0x7086 24 Input, 24 Output, 60 V, Ch-Ch Isolated Digital I/O
CWrite(0x10,0x000D0000) //Write the address to which you want to re-map the
PCI MITE to PCI configuration space offset 0x10
(BAR0).
Write(0xD0340,0x0000AEAE) //Write the value 0x0000AEAE to offset 0x340 from the
new PCI MITE address.
Table 3-1. Static DIO Devices and IDs (Continued)
Device ID Description