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6-3
Digital Waveform Acquisition
You can acquire digital waveforms on the Port 0 DIO lines. The DI waveform acquisition FIFO
stores the digital samples. M Series devices have a DMA controller dedicated to moving data
from the DI waveform acquisition FIFO to system memory. The DAQ device samples the DIO
lines on each rising or falling edge of a clock signal, DI Sample Clock.
You can configure each DIO line to be an output, a static input, or a digital waveform acquisition
input.
M Series devices feature the
digital input timing signal.
DI Sample Clock Signal
Use the DI Sample Clock (di/SampleClock) signal to sample the P0.<0..31> terminals and store
the result in the DI waveform acquisition FIFO. M Series devices do not have the ability to
divide down a timebase to produce an internal DI Sample Clock for digital waveform
acquisition. Therefore, you must route an external signal or one of many internal signals from
another subsystem to be the DI Sample Clock. For example, you can correlate digital and analog
samples in time by sharing your AI Sample Clock or AO Sample Clock as the source of your DI
Sample Clock. To sample a digital signal independent of an AI, AO, or DO operation, you can
configure a counter to generate the desired DI Sample Clock or use an external signal as the
source of the clock.
If the DAQ device receives a DI Sample Clock when the FIFO is full, it reports an overflow error
to the host software.
Using an Internal Source
To use DI Sample Clock with an internal source, specify the signal source and the polarity of the
signal. The source can be any of the following signals:
•
AI Sample Clock (ai/SampleClock)
•
AI Convert Clock (ai/ConvertClock)
•
AO Sample Clock (ao/SampleClock)
•
Counter
n
Internal Output
•
Frequency Output
•
DI Change Detection Output
Several other internal signals can be routed to DI Sample Clock through RTSI. Refer to
Device
Routing in MAX
in the
NI-DAQmx Help
or the
LabVIEW Help
for more information.
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