National Instruments PCI-6281, Руководство пользователя

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B-4
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Appendix B Timing Diagrams
Figure B-2. Input Timing and the Analog Input Timing Engine
Figure B-3. Input Timing Diagram
Table B-1. Input Timing
Time From To Min (ns) Max (ns)
t
1
*
PFI PFI_i 4.2 6.4 15.2 19.2
RTSI RTSI_i 0.9 2.2 2.0 3.0
STAR STAR_i 0.9 — — 2.8
*
The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the
trigger group for a given condition (maximum or minimum timing). This difference can be useful when
two external signals will be used together and the relative timing between the signals is important.
S t a rt Trigger
Termin a l
S elected Reference Trigger Reference Trigger
Termin a l
Termin a l
S elected Sa mple Clock
Termin a l
Termin a l
Termin a l
S elected S t a rt Trigger
RT S I
Termin a l
Termin a l
Termin a l
S elected P aus e Trigger
S I
Co u nter
Block
S I2
Co u nter
Block
S I_TC
Sa mple Clock Time bas e
S ync Sa mple Clock Time bas e
Convert Clock Time bas e
S ync Convert Clock Time bas e
S I S t a rt
P aus e Trigger
p_AI_Convert
S t a rt
1
S I2_TC
_i
_i
_i
_i
_i
Termin a l
_i
t
1
t
1