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Appendix C

National Instruments Corporation

C-21

PC-DIO-24/PnP User Manual

Main() {

#define BASE_ADDRESS

0x180

/* Board located at address 180 */

#define PORTAoffset

0x00

/* Offset for port A */

#define PORTBoffset

0x01

/* Offset for port B */

#define PORTCoffset

0x02

/* Offset for port C */

#define CNFGoffset

0x03

/* Offset for CNFG */

#define IREG1offset

0x14

/* Offset for Interrupt Reg. 1 */

#define IREG2offset

0x15

/* Offset for Interrupt Reg. 2 */

unsigned int porta, portb, portc, cnfg, ireg1, ireg2;

char valread;

/* Variable to store data read from a port */

/* Calculate register addresses */

porta = BASE_A PORTAoffset;

portb = BASE_A PORTBoffset;

portc = BASE_A PORTCoffset;

cnfg = BASE_A CNFGoffset;

ireg1 = BASE_A IREG1offset;

ireg2 = BASE_A IREG2offset;

/* EXAMPLE 1–Set up interrupts for mode 1 input for port A. Enable the

appropriate interrupt bits. */

outp(cnfg,0xB0);

/* Port A is an input in mode 1. */

outp(cnfg,0x09);

/* Set PC4 to enable interrupts from 82C55A. */

outp(ireg1,0x01);

/* Set IRQ0 to enable port A interrupts. */

outp(ireg2,0x04);

/* Set INTEN bit. */

/* EXAMPLE 2–Set up interrupts for mode 1 input for port B. Enable the

appropriate interrupt bits. */

outp(cnfg,0x86);

/* Port B is an input in mode 1. */

outp(cnfg,0x05);

/* Set PC2 to enable interrupts from 82C55A. */

outp(ireg1,0x02);

/* Set IRQ1 to enable port B interrupts. */

outp(ireg2,0x04);

/* Set INTEN bit. */

/* EXAMPLE 3–Set up interrupts for mode 1 output for port A. Enable the

appropriate interrupt bits. */

outp(cnfg,0xA0);

/* Port A is an output in mode 1. */

outp(cnfg,0x0D);

/* Set PC6 to enable interrupts from 82C55A. */

outp(ireg1,0x01);

/* Set IRQ0 to enable port A interrupts. */

outp(ireg2,0x04);

/* Set INTEN bit. */

/* EXAMPLE 4–Set up interrupts for mode 1 output for port B. Enable the

appropriate interrupt bits. */

outp(cnfg,0x84);

/* Port B is an output in mode 1. */

outp(cnfg,0x05);

/* Set PC2 to enable interrupts from 82C55A. */

Содержание PC-DIO-24/PnP

Страница 1: ...d for ISA Computers February 1998 Edition Part Number 320288C 01 Copyright 1989 1998 National Instruments Corporation All rights reserved Click here to comment on this document via the National Instruments website at www natinst com documentation daq ...

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Страница 3: ...R CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to ...

Страница 4: ...ergy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Notice to User Changes or modifications not expressly approved by National Instruments coul...

Страница 5: ... to Get Started 1 2 Software Programming Choices 1 2 National Instruments Application Software 1 2 NI DAQ Driver Software 1 3 Register Level Programming 1 4 Optional Equipment 1 5 Custom Cables 1 5 Unpacking 1 7 Chapter 2 Installation and Configuration Installation 2 1 Hardware Configuration 2 2 Plug and Play 2 2 Base I O Address and Interrupt Selection 2 3 Chapter 3 Signal Connections I O Connect...

Страница 6: ...2 82C55A Programmable Peripheral Interface 4 2 Digital I O Connector 4 3 Appendix A Specifications Appendix B OKI 82C55A Data Sheet Appendix C Register Level Programming Introduction C 1 Register Map C 3 Register Description for the 82C55A C 3 Register Description for the Interrupt Control Registers C 5 Interrupt Control Register 1 PnP Board Only C 6 Interrupt Control Register 2 PnP Board Only C 7...

Страница 7: ...s D 3 Interrupt Selection D 5 Interrupt Enable Settings D 6 Interrupt Level Settings D 6 Installation D 7 Appendix E Customer Communication Glossary Index Figures Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware 1 4 Figure 2 1 Jumper W1 Location 2 1 Figure 3 1 Digital I O Connector Pin Assignments 3 2 Figure 3 2 Digital I O Connections 3 6 Figure 3 3 DIO Cha...

Страница 8: ...igure D 1 PC DIO 24 Parts Locator Diagram D 3 Figure D 2 Example Base I O Address Switch Settings D 4 Figure D 3 Interrupt Enable Jumper Settings D 6 Figure D 4 Interrupt Jumper Setting for IRQ5 Factory Setting D 6 Tables Table 3 1 Signal Descriptions 3 3 Table 3 2 Port C Signal Assignments 3 4 Table 3 3 Timing Signal Descriptions 3 10 Table C 1 PC DIO 24 PnP Address Map C 3 Table C 2 Port C Set R...

Страница 9: ...ur PC DIO 24 Non PnP Board Organization of This Manual The PC DIO 24 PnP User Manual is organized as follows Chapter 1 Introduction describes the PC DIO 24 PnP lists what you need to get started describes software programming choices optional equipment and custom cables and explains how to unpack the PC DIO 24 PnP Chapter 2 Installation and Configuration describes how to install and configure the ...

Страница 10: ... alphabetically lists the topics in this manual including the page where you can find each one Conventions Used in This Manual The following conventions are used in this manual This icon to the left of bold italicized text denotes a note which alerts you to important information This icon to the left of bold italicized text denotes a caution which advises you of precautions to take to avoid injury...

Страница 11: ...O 24 PnP refers to both the Plug and Play and non Plug and Play compatible versions of the board PC DIO 24PnP PC DIO 24PnP refers to the Plug and Play version of the board PC DIO 24 PC DIO 24 refers to the non Plug and Play version of the board PnP PnP Plug and Play refers to a device that is fully compatible with the industry standard Plug and Play ISA Specification non PnP Non PnP refers to a de...

Страница 12: ...iled information about the DAQ hardware that plugs into or is connected to your computer Use these manuals for hardware installation and configuration instructions specification information about your DAQ hardware and application hints Software documentation Examples of software documentation you may have are the LabVIEW and LabWindows CVI manual sets and the NI DAQ documentation After you set up ...

Страница 13: ...lug and Play ISA Specification Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with them To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix E Custom...

Страница 14: ...rate interrupt requests to the host computer You can program the 82C55A chip for numerous 8 bit 16 bit or 24 bit digital I O applications All digital I O communication is through a standard 50 pin male connector The pin assignments for this connector are compatible with standard 24 channel digital I O applications PnP refers to the Plug and Play technology used in this board See the definition in ...

Страница 15: ... DAQ or register level programming National Instruments Application Software ComponentWorks contains tools for data acquisition and instrument control built on NI DAQ driver software ComponentWorks provides a higher level programming interface for building virtual instruments through standard OLE controls and DLLs With ComponentWorks you can use all of the configuration tools resource management u...

Страница 16: ...nentWorks LabVIEW LabWindows CVI or VirtualBench software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include ...

Страница 17: ...e very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer consider using National Instruments application software to program your National Instruments DAQ hardware Using the National Instruments application software is easier than and as flexible as register level programming and can save weeks of development time Componen...

Страница 18: ... Instruments catalogue or call the office nearest you Note The PC DIO 24 PnP can drive the SSR ODC 5 output module and all SSR input modules available from National Instruments but cannot reliably sink sufficient current to drive the SSR OAC 5 and SSR OAC 5A output modules To drive a SSR OAC 5 or SSR OAC 5A you can either use a non inverting digital buffer chip between the PC DIO 24 PnP and the SS...

Страница 19: ...are as follows Electronic Products Division 3M part number 3365 50 T B Ansley Corporation part number 171 50 Recommended manufacturer part numbers for the 50 pin edge connector for connecting to a module rack with an edge connector are as follows Electronic Products Division 3M part number 3415 0001 T B Ansley Corporation part number 622 5015 A polarizing key can be plugged into these edge connect...

Страница 20: ...e in handling the board take the following precautions Ground yourself via a grounding strap or by holding a grounded object Touch the antistatic package to a metal part of your PC chassis before removing the board from the package Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any...

Страница 21: ...DIO 24 PnP uses 100 kΩ resistors for polarity selection at power up You can use jumper W1 to select whether data signals are pulled up to Vcc 5 VDC factory default or pulled down to GND Figure 2 1 shows jumper W1 For more information see the Digital I O Power up State Selection section in Chapter 3 Signal Connections You can install the PC DIO 24 PnP in any unused 8 or 16 bit expansion slot in you...

Страница 22: ...guration Plug and Play The PC DIO 24PnP is fully compatible with the industry standard Intel Microsoft Plug and Play Specification A Plug and Play system arbitrates and assigns resources through software freeing you from manually setting switches and jumpers These resources include the PC DIO 24PnP base I O address and interrupt channel The Configuration Manager receives all of the resource reques...

Страница 23: ...uration Utility Help file You can configure the PC DIO 24PnP to use base addresses in the range of 100 to 3E0 hex Each board occupies 32 bytes of address space and must be located on a 32 byte boundary Therefore valid addresses include 100 120 140 3E0 hex The PC DIO 24PnP can use interrupt channel 3 4 5 7 or 9 Note To configure the non Plug and Play PC DIO 24 board refer to Appendix D Using Your P...

Страница 24: ...n Connections that exceed any of the maximum ratings of input or output signals on the PC DIO 24 PnP can damage the board and the PC National Instruments is NOT liable for any damages resulting from any such signal connections Maximum ratings for each signal are given in this chapter under the discussion of that signal I O Connector Figure 3 1 shows the pin assignments for the PC DIO 24 PnP digita...

Страница 25: ... 5 V PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 49 50 47 48 45 46 43 44 41 42 39 40 37 38 35 36 33 34 31 32 29 30 27 28 25 26 23 24 21 22 19 20 17 18 15 16 13 14 11 12 9 10 7 8 5 6 3 4 1 2 ...

Страница 26: ...t Table 3 2 summarizes the signal assignments of port C for each programmable mode Ports A and B can be in different modes the table does not show every possible combination See Appendix C Register Level Programming for register level programming information Table 3 1 Signal Descriptions Pin Signal Name Description 1 3 5 7 9 11 13 15 PC 7 0 Port C Bidirectional data lines for port C PC7 is the MSB...

Страница 27: ... Digital input specifications referenced to GND Input logic high voltage 2 2 V min 5 3 V max Input logic low voltage 0 3 V min 0 8 V max Input high current Vin 5 V W1 set to pullup 11 0 µA max Input high current Vin 5 V W1 set to pulldown 65 µA max Input logic low current Vin 0 V W1 set to pullup 65 µA max Input logic low current Vin 0 V W1 set to pulldown 11 µA max Table 3 2 Port C Signal Assignm...

Страница 28: ...cations referenced to GND Output logic high voltage 3 7 V min 5 0 V max Iol 2 5 mA Output logic high voltage 2 7 V min 5 0 V max Ioh 4 mA Output logic low voltage 0 V min 0 4 V Iol 2 5 mA Output logic low voltage 0 V min 0 5 V Iol 4 mA Figure 3 2 depicts signal connections for three typical digital I O applications ...

Страница 29: ...ions include receiving TTL signals and sensing external device states such as the state of the switch in Figure 3 2 Digital output applications include sending TTL signals and driving external devices such as the LED shown in this figure PC DIO 24 PnP I O Connector 5 V 5 V LED TTL Signal 41 43 45 47 67 71 73 69 50 100 5 V Jumper Selectable W1 100 kΩ 100 kΩ 100 kΩ 100 kΩ 100 kΩ 100 kΩ 100 kΩ 100 kΩ...

Страница 30: ...r configurable pull up or pull down Each DIO channel is connected to a 100 kΩ resistor and can be pulled high or low using jumper W1 You can use W1 to pull all 24 DIO lines high or low However you may want to pull individual lines in different directions To do this properly you must understand the nature of the drive current on those lines and adhere to TTL logic levels High DIO Power up State If ...

Страница 31: ...ogic low level of 0 4 V with a minimum reduction to the DIO drive current V I RL RL V I where V 0 4 V Voltage across RL I 46 µA 11 µA 4 6 V across the 100 kΩ pull up resistor and 11 µA max leakage current Therefore RL 7 0 kΩ 0 4 V 57 µA This resistor value 7 0 kΩ provides a maximum of 0 4 V on the DIO line at power up You can substitute smaller resistor values to lower the voltage or to provide a ...

Страница 32: ...along with the current from the 100 kΩ pull down resistor brings the voltage at the resistor below a TTL high level of 2 8 VDC Figure 3 4 DIO Channel Configured for Low DIO Power up State with External Load Example At power up the board is configured for input and jumper W1 is set in the low DIO power up state which means all DIO lines are pulled low If you want to pull one channel high follow the...

Страница 33: ...dshaking lines OBF and ACK synchronize output transfers The signals in Table 3 3 are used in the timing diagrams on the subsequent pages Table 3 3 Timing Signal Descriptions Name Signal Direction Description STB Input Strobe Input A low signal on this handshaking line loads data into the input latch IBF Output Input Buffer Full A high signal on this handshaking line indicates that data has been lo...

Страница 34: ...rate this signal RD Internal Read Signal This signal is the read signal generated from the control lines of the PC WR Internal Write Signal This signal is the write signal generated from the control lines of the PC DATA Bidirectional Data Lines at the Selected Port This signal indicates when the data on the data lines at a selected port is available output or should be available input Table 3 3 Ti...

Страница 35: ...ations for an input transfer in mode 1 Figure 3 5 Mode 1 Timing Specification for Input Transfers Name Description Minimum Maximum T1 STB pulse width 100 T2 STB 0 to IBF 1 150 T3 Data before STB 1 20 T4 STB 1 to INTR 1 150 T5 Data after STB 1 50 T6 RD 0 to INTR 0 200 T7 RD 1 to IBF 0 150 All timing values are in nanoseconds T3 T5 T6 T7 T4 T1 T2 STB IBF INTR RD DATA ...

Страница 36: ...ming specifications for an output transfer in mode 1 Figure 3 6 Mode 1 Timing Specification for Output Transfers Name Description Minimum Maximum T1 WR 0 to INTR 0 250 T2 WR 1 to output 200 T3 WR 1 to OBF 0 150 T4 ACK 0 to OBF 1 150 T5 ACK pulse width 100 T6 ACK 1 to INTR 1 150 All timing values are in nanoseconds T2 T3 WR OBF INTR DATA T4 T6 T5 ACK T1 ...

Страница 37: ...3 7 Mode 2 Timing Specification for Bidirectional Transfers Name Description Minimum Maximum T1 WR 1 to OBF 0 150 T2 Data before STB 1 20 T3 STB pulse width 100 T4 STB 0 to IBF 1 150 T5 Data after STB 1 50 T6 ACK 0 to OBF 1 150 T7 ACK pulse width 100 T8 ACK 0 to output 150 T9 ACK 1 to output float 20 250 T10 RD 1 to IBF 0 150 All timing values are in nanoseconds T2 T1 WR OBF INTR ACK DATA T6 T7 T3...

Страница 38: ...igure 4 1 illustrates the key functional components of the PC DIO 24 PnP board Figure 4 1 PC DIO 24 PnP Block Diagram The PC I O channel consists of an address bus a data bus interrupt lines and several control and support signals Control and data transfers to the system microprocessor are asynchronous I O Connector Interrupt Control Circuitry 82C55A PPI Bus Transceivers 8 8 8 5 V PC I O Channel 1...

Страница 39: ...e interrupt circuitry The PC DIO 24 non PnP uses one of the extra PC lines jumper selectable as an interrupt enable 82C55A Programmable Peripheral Interface The 82C55A PPI chip is the heart of the PC DIO 24 PnP This chip has 24 programmable I O pins that represent three 8 bit ports PA PB and PC You can program each port as an input or an output port The 82C55A has three modes of operation simple I...

Страница 40: ...ted through a standard 50 pin male connector Pin 49 is connected to 5 V through a resettable protection fuse You can use this 5 V supply to operate I O module mounting racks Even numbered pins are connected to ground See the Optional Equipment section in Chapter 1 Introduction as well as Chapter 3 Signal Connections for additional information ...

Страница 41: ...ompatibility TTL Absolute max voltage input rating Vcc 5 0 V 0 5 to 5 5 V with respect to GND Handshaking Requires one port Power on state Configured as inputs pulled high or low jumper selectable Data transfers Interrupts programmed I O Digital Logic Levels Input Signals The maximum input logic high and output logic high voltages assume a Vcc supply voltage of 5 0 V Level Min Max Input logic high...

Страница 42: ... 2 in I O connector 50 pin male ribbon cable connector Input high current Vin 5 V W1 set to pulldown 65 µA Input logic low current Vin 0 V W1 set to pullup 65 µA Input logic low current Vin 0 V W1 set to pulldown 11 µA Level Min Max Output logic high voltage Iol 2 5 mA 3 7 V 5 0 V Output logic high voltage Ioh 4 mA 2 7 V 5 0 V Output logic low voltage Iol 2 5 mA 0 V 0 4 V Output logic low voltage ...

Страница 43: ... 24 PnP transfer rates Computer system performance Programming environment register level programming or NI DAQ Programming language and code efficiency Execution mode foreground or background with background execution typically using interrupts Other operations in progress Application For example you can obtain higher transfer rates in a handshaking or data transfer application requiring an avera...

Страница 44: ...ppendix contains the manufacturer data sheet for the OKI Semiconductor 82C55A CMOS PPI This interface is used on the PC DIO 24 PnP board Copyright OKI Semiconductor 1995 Reprinted with permission of copyright owner All rights reserved OKI Semiconductor Data Book Microprocessor Eighth Edition January 1995 ...

Страница 45: ...Appendix B OKI 82C55A Data Sheet PC DIO 24 PnP User Manual B 2 National Instruments Corporation ...

Страница 46: ...Appendix B OKI 82C55A Data Sheet National Instruments Corporation B 3 PC DIO 24 PnP User Manual ...

Страница 47: ...Appendix B OKI 82C55A Data Sheet PC DIO 24 PnP User Manual B 4 National Instruments Corporation ...

Страница 48: ...Appendix B OKI 82C55A Data Sheet National Instruments Corporation B 5 PC DIO 24 PnP User Manual ...

Страница 49: ...Appendix B OKI 82C55A Data Sheet PC DIO 24 PnP User Manual B 6 National Instruments Corporation ...

Страница 50: ...Appendix B OKI 82C55A Data Sheet National Instruments Corporation B 7 PC DIO 24 PnP User Manual ...

Страница 51: ...Appendix B OKI 82C55A Data Sheet PC DIO 24 PnP User Manual B 8 National Instruments Corporation ...

Страница 52: ...Appendix B OKI 82C55A Data Sheet National Instruments Corporation B 9 PC DIO 24 PnP User Manual ...

Страница 53: ...Appendix B OKI 82C55A Data Sheet PC DIO 24 PnP User Manual B 10 National Instruments Corporation ...

Страница 54: ...Appendix B OKI 82C55A Data Sheet National Instruments Corporation B 11 PC DIO 24 PnP User Manual ...

Страница 55: ...Appendix B OKI 82C55A Data Sheet PC DIO 24 PnP User Manual B 12 National Instruments Corporation ...

Страница 56: ...Appendix B OKI 82C55A Data Sheet National Instruments Corporation B 13 PC DIO 24 PnP User Manual ...

Страница 57: ...Appendix B OKI 82C55A Data Sheet PC DIO 24 PnP User Manual B 14 National Instruments Corporation ...

Страница 58: ...Appendix B OKI 82C55A Data Sheet National Instruments Corporation B 15 PC DIO 24 PnP User Manual ...

Страница 59: ...Appendix B OKI 82C55A Data Sheet PC DIO 24 PnP User Manual B 16 National Instruments Corporation ...

Страница 60: ...Appendix B OKI 82C55A Data Sheet National Instruments Corporation B 17 PC DIO 24 PnP User Manual ...

Страница 61: ...id addresses include 100 120 140 3E0 hex The base I O address is software configured and does not require you to manually change any board settings For more information on configuring the PC DIO 24PnP see Chapter 2 Installation and Configuration The PC DIO 24 non PnP board occupies four bytes of address space and must be located on a four byte boundary For more information on configuring the PC DI...

Страница 62: ...group A control bits configure port A A7 through A0 and the upper 4 bits nibble of port C C7 through C4 The group B control bits configure port B B7 through B0 and the lower nibble of port C C3 through C0 These configuration bits are defined in the Register Description for the 82C55A section later in this appendix The 82C55A potentially requires up to 200 ns recovery time between consecutive read ...

Страница 63: ...6 through 0 select the I O characteristics of the 82C55A ports These bits also select the mode in which the ports are operating that is mode 0 mode 1 or mode 2 When the control word flag is 0 bits 3 through 0 select the bit set reset format of port C Table C 1 PC DIO 24 PnP Address Map Register Name Offset Address Hex Size Type 82C55A Register Group PORTA Register 00 8 bit Read and write PORTB Reg...

Страница 64: ...tput port B is undefined D2 D1 D0 D5 D4 D3 D7 D6 high nibble 1 input 0 output Control Word Flag 1 mode set 00 mode 0 01 mode 1 1X mode 2 Mode Selection 1 input 0 output Port A Port C low nibble 1 input 0 output Port C 0 mode 0 1 mode 1 Mode Selection Group A Group B Port B 1 input 0 output Flag D2 D1 D0 D3 D7 0 bit set reset 1 set 0 reset 000 001 010 111 Control Word Bit Select Bit Set Reset a Mod...

Страница 65: ...e registers has individual enable bits for the two interrupt lines from the 82C55A device The other register has a master interrupt enable bit When writing to these registers set all reserved bits to zero The bit maps and signal definitions are listed as follows Table C 2 Port C Set Reset Control Words Bit Number Bit Set Control Word Bit Reset Control Word The Bit Set or Reset in Port C 0 0xxx0001...

Страница 66: ... can send an interrupt INTRB to the host computer If this bit is cleared the PPI does not send the interrupt INTRB to the host computer regardless of the setting of INTEN 0 IRQ0 PPI Interrupt Request for Port A If this bit and the INTEN bit in Interrupt Control Register 2 are both set the PPI can send an interrupt INTRA to the host computer If this bit is cleared the PPI does not send the interrup...

Страница 67: ...Interrupt Control Register 2 PnP Board Only Bit Name Description 1 0 3 7 X Reserved Bit 2 INTEN Global Interrupt Enable Bit If this bit is set the PC DIO 24PnP can interrupt the host computer If this bit is cleared the board cannot interrupt the host computer D7 D6 D5 D4 D3 D2 D1 D0 X X X X X INTEN X X ...

Страница 68: ...data from a specified port Mode 0 has the following features Two 8 bit ports A and B and two 4 bit ports upper and lower nibbles of port C Any port can be input or output Outputs are latched but inputs are not latched Mode 1 This mode transfers data that is synchronized by handshaking signals Ports A and B use the eight lines of port C to generate or receive the handshake signals This mode divides...

Страница 69: ...ntrol signals for port A and port B when these ports are operating in mode 1 or mode 2 Mode 0 Basic I O Use mode 0 for simple I O functions no handshaking for each of the three ports You can assign each port as an input or an output port The 16 possible I O configurations are shown in Table C 3 Notice that bit 7 of the control word is set when programming the mode of operation for each port Table ...

Страница 70: ...orta portb portc cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE_ADDRESS PORTAoffset portb BASE_ADDRESS PORTBoffset portc BASE_ADDRESS PORTCoffset cnfg BASE_ADDRESS CNFGoffset EXAMPLE 1 outp cnfg 0x80 Ports A B and C are outputs outp porta 0x12 Write data to port A outp portb 0x34 Write data to port B 9 10010001 Input Output Output Input 10 1001001...

Страница 71: ... an input Mode 1 Strobed Input In mode 1 the digital I O bits are divided into two groups group A and group B Each of these groups contains one 8 bit port and one 3 bit control data port The 8 bit port can be either an input or an output port and the 3 bit port is used for control and status information for the 8 bit port The transfer of data is synchronized by handshaking signals in the 3 bit por...

Страница 72: ... A is in mode 1 input If these bits are configured for output the port C bit set reset function must be used to manipulate them 5 IBFA Input Buffer for Port A A high setting indicates that data has been loaded into the input latch for port A 4 INTEA Interrupt Enable Bit for Port A Setting this bit enables interrupts from port A of the 82C55A This bit is controlled by setting resetting PC4 3 INTRA ...

Страница 73: ...mple shows how to configure PPI A for various combinations of mode 1 input This code is strictly an example and is not intended to be used without modification in a practical situation Main define BASE_ADDRESS 0x180 Board located at address 180 define PORTAoffset 0x00 Offset for port A define PORTBoffset 0x01 Offset for port B define PORTCoffset 0x02 Offset for port C define CNFGoffset 0x03 Offset...

Страница 74: ...itten to the CNFG Register to configure port A for output in mode 1 is shown as follows Bits PC4 and PC5 of port C can be used as extra input or output lines The control word written to the CNFG Register to configure port B for output in mode 1 is shown as follows Notice that port B does not have extra input or output lines left from port C when ports A and B are both enabled for handshaking Durin...

Страница 75: ...used to manipulate them 3 INTRA Interrupt Request Status for Port A When INTEA and OBFA are high this bit is high indicating that an interrupt request is pending for port A 2 INTEB Interrupt Enable Bit for Port B Setting this bit enables interrupts from port B of the 82C55A This bit is controlled by setting resetting PC2 1 OBFB Output Buffer for Port B A low setting indicates that the CPU has writ...

Страница 76: ...et for port A define PORTBoffset 0x01 Offset for port B define PORTCoffset 0x02 Offset for port C define CNFGoffset 0x03 Offset for CNFG unsigned int porta portb portc cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE_ADDRESS PORTAoffset portb BASE_ADDRESS PORTBoffset portc BASE_ADDRESS PORTCoffset cnfg BASE_ADDRESS CNFGoffset EXAMPLE 1 port A output...

Страница 77: ...configuration The data transfers are synchronized with handshaking lines in port C This mode uses only port A however port B can be used in either mode 0 or mode 1 while port A is configured for mode 2 The control word written to the CNFG Register to configure port A as a bidirectional data bus in mode 2 is shown as follows If port B is configured for mode 0 then PC2 PC1 and PC0 of port C can be u...

Страница 78: ...ting PC6 5 IBFA Input Buffer for Port A A high setting indicates that data has been loaded into the input latch of port A 4 INTE2 Interrupt Enable Bit for Port A Input Interrupts Setting this bit enables input interrupts from port A of the 82C55A This bit is controlled by setting resetting PC4 3 INTRA Interrupt Request Status for Port A If INTE1 and IBFA are high then this bit is high indicating t...

Страница 79: ...ADDRESS 0x180 Board located at address 180 define PORTAoffset 0x00 Offset for port A define PORTBoffset 0x01 Offset for port B define PORTCoffset 0x02 Offset for port C define CNFGoffset 0x03 Offset for CNFG unsigned int porta portb portc cnfg char valread Variable to store data read from a port Calculate register addresses porta BASE_ADDRESS PORTAoffset portb BASE_ADDRESS PORTBoffset portc BASE_A...

Страница 80: ...errupts with the PC3 or PC0 lines of the 82C55A devices you must maintain the active high level until the interrupt service routine is entered Otherwise the host computer considers the interrupt a spurious interrupt and routes the request to the channel responsible for handling spurious interrupts To prevent this problem try using some other I O bit to send feedback to the device generating the in...

Страница 81: ...ut for port A Enable the appropriate interrupt bits outp cnfg 0xB0 Port A is an input in mode 1 outp cnfg 0x09 Set PC4 to enable interrupts from 82C55A outp ireg1 0x01 Set IRQ0 to enable port A interrupts outp ireg2 0x04 Set INTEN bit EXAMPLE 2 Set up interrupts for mode 1 input for port B Enable the appropriate interrupt bits outp cnfg 0x86 Port B is an input in mode 1 outp cnfg 0x05 Set PC2 to e...

Страница 82: ...pendix D Using Your PC DIO 24 Non PnP Board On the PC DIO 24PnP the INTEN bit of Interrupt Register 2 must be set to enable interrupts This bit must first be cleared to disable unwanted interrupts After all sources of interrupts have been disabled or placed in an inactive state you can set INTEN To interrupt the host computer program the selected 82C55A port for the I O mode desired In mode 1 set ...

Страница 83: ...RQ0 if you are using PC0 set IRQ1 When the external signal becomes logic high an interrupt request occurs Although the host computer s interrupt monitoring circuitry is triggered by the positive going edge of the interrupt signal the signal must remain high until the interrupt routine has been entered and interrupts have been masked out Make sure your external interrupt signal meets these qualific...

Страница 84: ...resses and interrupt levels The original legacy board was replaced with a backwards compatible revised PC DIO 24 that has many of the new features of the Plug and Play version The following list compares the specifications and functionality of the newer boards with the original legacy board This document applies only to the revised PC DIO 24 PnP board Table D 1 Comparison of Characteristics Specif...

Страница 85: ... or interrupt level you need to change these settings on the PC DIO 24 as described in the following pages or on the other hardware Record your settings in the PC DIO 24 PnP Hardware and Software Configuration Form in Appendix E Customer Communication 5 V supply fuse Nonresettable Self resetting Self resetting Power up state No pullups or pulldowns Jumper for pullup factory default or pulldown Jum...

Страница 86: ...change the base I O address for the PC DIO 24 or for the other device Each switch in U9 corresponds to one of the address lines A9 through A2 For space reasons not all address lines are separately labeled on the board The range for possible base I O address settings is hex 000 through 3FC Base I O address values hex 000 through 0FF are reserved for system use Base I O values hex 100 through 3FF ar...

Страница 87: ... 2 Example Base I O Address Switch Settings Table D 3 shows some examples of switch settings and their corresponding address ranges U9 A9 A8 A7 A6 A5 A4 A3 A2 1 2 3 4 5 6 7 8 b Switches Set to Base I O Address Hex 278 U9 A9 A8 A7 A6 A5 A4 A3 A2 1 2 3 4 5 6 7 8 a Switches Set to Base I O Address Hex 210 Default Setting ...

Страница 88: ...I O Address Space Used hex A9 A8 A7 A6 A5 A4 A3 A2 0 1 0 0 0 0 0 0 100 100 103 0 1 0 0 1 0 0 0 120 120 123 0 1 0 1 0 0 0 0 140 140 143 0 1 0 1 1 0 0 0 160 160 163 0 1 1 0 0 0 0 0 180 180 183 0 1 1 0 1 0 0 0 1A0 1A0 1A3 0 1 1 1 0 0 0 0 1C0 1C0 1C3 0 1 1 1 1 0 0 0 1E0 1E0 1E3 1 0 0 0 0 0 0 0 200 200 203 1 0 0 0 1 0 0 0 220 220 223 1 0 0 1 0 0 0 0 240 240 243 1 0 0 1 1 0 0 0 260 260 263 1 0 1 0 0 0 0...

Страница 89: ...quests from the board are enabled and controlled by PC4 Figure D 3 Interrupt Enable Jumper Settings Interrupt Level Settings The PC DIO 24 board can connect to any one of the six interrupt lines of the PC I O Channel IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 or IRQ9 You select the interrupt line by setting a jumper on W2 To use the interrupt capability of the board select an interrupt line and place the jumper in ...

Страница 90: ...stall the PC DIO 24 as described in Chapter 2 Installation and Configuration If you have an ISA class computer and you are using a configurable software package such as NI DAQ you may need to reconfigure your software to reflect any changes in jumper or switch settings If you have an EISA class computer you need to update the computer resource allocation or configuration table by reconfiguring you...

Страница 91: ...ephone support through our technical support centers which are staffed by applications engineers Electronic Services Bulletin Board Support National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of files and documents to answer most common customer questions From these sites you can also download the latest instrument drivers updates and example programs For rec...

Страница 92: ...btain support Country Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 79 90 19 Belgium 02 757 00 20 02 757 03 11 Brazil 011 288 3336 011 288 8528 Canada Ontario 905 785 0085 905 785 0086 Canada Québec 514 694 8521 514 694 4399 Denmark 45 76 26 00 45 76 26 02 Finland 09 725 725 11 09 725 725 55 France 01 48 14 24 24 01 48 14 24 14 Germany 089 741 31 30 089 714 60 3...

Страница 93: ..._______________________________________________________________________ National Instruments hardware product model __________ Revision ______________________ Configuration ___________________________________________________________________ National Instruments software product ____________________________Version ____________ Configuration __________________________________________________________...

Страница 94: ...hannels of other boards _______________________________________________________ Interrupt levels of other boards _______________________________________________________ Other Products Computer make and model _________________________________________________________ Microprocessor ___________________________________________________________________ Clock frequency or speed __________________________...

Страница 95: ..._____________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ _______________________________________________________________________________ __...

Страница 96: ...grees negative of or minus Ω ohms per percent positive of or plus A A ampere AC alternating current address character code that identifies a specific location or series of locations in memory AWG American Wire Gauge Prefix Meanings Value µ micro 10 6 m milli 10 3 k kilo 103 M mega 106 ...

Страница 97: ...the base address BCD binary coded decimal C C Celsius channel pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels D D A digital to analog data acquisition 1 collecting and measuring electrical sign...

Страница 98: ...x hexadecimal Hz hertz the number of scans read or updates written per second I in inches Iin input current Iout output current interrupt a computer signal indicating that the CPU should suspend its current task to service a designated activity interrupt level the relative priority at which a device can interrupt I O input output the transfer of data to from a computer system involving communicati...

Страница 99: ...t M m meters M 1 Mega the standard metric prefix for 1 million or 106 when used with units of measure such as volts and hertz 2 mega the prefix for 1 048 576 or 220 when used with B to quantify data or computer memory MB megabytes of memory MSB most significant bit N NI DAQ National Instruments driver software for DAQ hardware O operating system base level software that controls a computer runs pr...

Страница 100: ...nd or output R RAM random access memory resolution the smallest signal increment that can be detected by a measurement system Resolution can be expressed in bits in proportions or in percent of full scale For example a system has 12 bit resolution one part in 4 096 resolution and 0 0244 of full scale REXT external resistance S s seconds S samples SCXI Signal Conditioning eXtensions for Instrumenta...

Страница 101: ...plies to its plug in devices VDC volts direct current VEXT external volt VI virtual instrument 1 a combination of hardware and or software elements typically used with a PC that has the functionality of a classic stand alone instrument 2 a LabVIEW software module VI which consists of a front panel user interface and a block diagram program ...

Страница 102: ...e I O address settings PC DIO 24 non PnP D 3 to D 5 example settings figure D 4 example settings with corresponding base I O address and address space table D 5 factory settings table D 2 in use by other equipment note D 3 PC DIO 24 PnP selecting 2 3 valid addresses C 1 block diagram of PC DIO 24 PnP 4 1 board configuration See configuration bulletin board support E 1 bus interface 4 2 bus transce...

Страница 103: ...nual x xi National Instruments documentation xii organization of manual ix x related documentation xiii E electronic support services E 1 e mail support E 2 environment specifications A 3 equipment optional 1 5 to 1 6 F fax and telephone number support E 2 Fax on Demand support E 2 FTP support E 1 fuse self resetting for 5 V signal 3 7 G GND signal table 3 2 I IBF signal description table 3 10 mod...

Страница 104: ...3 factory settings table D 2 interrupt enable settings D 6 interrupt level settings D 6 to D 7 jumper W1 data signal settings note 2 1 location of figure 2 1 jumper W2 location figure D 3 settings table D 2 jumper W3 location figure D 3 settings table D 2 L LabVIEW and LabWindows CVI application software 1 2 to 1 3 M manual See documentation modes of operation 82C55A mode 0 basic I O C 9 to C 11 c...

Страница 105: ...o D 7 base I O address settings D 3 to D 5 factory set jumper and switch settings table D 2 interrupt selection D 5 to D 7 parts locator diagram D 3 differences between PC DIO 24 PnP and D 1 to D 2 comparison of characteristics table D 1 to D 2 installation D 7 PC DIO 24 PnP block diagram 4 1 configuration 2 2 to 2 3 custom cables 1 5 to 1 6 installation 2 1 to 2 2 optional equipment 1 5 to 1 6 ov...

Страница 106: ...ntrol word written to CNFG Register figure C 17 Port C pin assignments figure C 19 Port C status word bit definitions C 18 programming example C 19 to C 20 overview C 1 to C 2 register descriptions C 3 to C 7 82C55A C 3 to C 5 control word formats figure C 4 interrupt control registers C 5 to C 7 Port C set reset control words table C 5 register map C 3 requirements for getting started 1 2 S self ...

Страница 107: ...gnal assignments table 3 4 switch settings See jumper and switch settings T technical support E 1 to E 2 telephone and fax number support E 2 theory of operation 4 1 to 4 3 82C55A Programmable Peripheral Interface 4 2 block diagram 4 1 bus interface 4 2 bus transceivers 4 2 digital I O connector 4 3 interrupt control circuitry 4 2 PC I O channel control circuitry 4 1 to 4 2 timing specifications 3...

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