National Instruments NI-5783, Руководство по началу работы

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Figure 2. NI 5783 Logic Layout
SPI
Reg Report
Microblaze
User
Command
Interface
FAM
Status
Registers
I
2
C
Data Clock Sample Clock
Data Clock 2x
1 Sample Per Channel
1/2 Samples Per Channel
Iserdes
ADC
Capture
EEPROM
Phase
DAC
PLL
DAC
User Diag
ram
Oserdes
Iserdes
Oserdes
DPA
Output
ADC
Clocking
Component-Level Intellectual Property (CLIP)
The LabVIEW FPGA Module includes component-level intellectual property (CLIP) for HDL
IP integration. FlexRIO devices support two types of CLIP: user-defined and socketed.
•
User-defined CLIP allows you to insert HDL IP into an FPGA target, enabling VHDL
code to communicate directly with an FPGA VI.
• Socketed CLIP provides the same IP integration of the user-defined CLIP, but it also
allows the CLIP to communicate directly with circuitry external to the FPGA. Adapter
module socketed CLIP allows your IP to communicate directly with both the FPGA VI
and the external adapter module connector interface.
The FlexRIO adapter module ships with socketed CLIP items that add module I/O to the
LabVIEW project.
NI 5783 CLIP
This CLIP provides access to four 16-bit 100 MS/s analog input channels, four 16-bit analog
output channels (selectable between 100 MS/s and 200 MS/s), eight bidirectional DIO
channels, four bidirectional PFI channels, and the front panel trigger.
The analog output channels can be written two samples at a time in the Data Clock domain
with 4x interpolation, one sample at a time in the Data Clock domain with 8x interpolation, or
one sample at a time in the Data Clock 2x domain with 4x interpolation, according to the clock
mode selected.
10 | ni.com | NI 5783 Getting Started Guide