National Instruments DAQ Series, Руководство пользователя

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Chapter 3 Connecting Signals
© National Instruments Corporation 3-19 DAQCard-700 User Manual
Figure 3-10 shows the timing requirements for the GATE and CLK input
signals and the timing specifications for the OUT output signals of the
MSM82C54.
Figure 3-10. General-Purpose Timing Signals
The GATE and OUT signals in Figure 3-10 are referenced to the rising edge
of the CLK signal.
Refer to Appendix A, Specifications , for more information about the
MSM82C54 DIO specifications.
CLK
GATE
OUT
V
IH
V
IL
V
IH
V
IL
V
OH
V
OL
sc pwh pwl
gsu gh
gwh gwl
outg outc
sc
pwh
pwl
gsu
gh
gwh
gwl
outc
outg
clock period
clock high level
clock low level
gate setup time
gate hold time
gate high level
gate low level
output delay from clock
output delay from gate
100 ns min
30 ns min
50 ns min
40 ns min
50 ns min
50 ns min
50 ns min
100 ns max
100 ns max