Chapter 2
Configuration and Installation
© National Instruments Corporation
2-23
SCXI-1162 User Manual
To write to the Address Handler, follow these steps:
1. Initial conditions:
SS* asserted low.
SERDATIN = don't care.
DAQD*/A = 1 (indicates data will be written to the Address Handler).
SLOT0SEL* = 1.
SERCLK = 1 (and has not transitioned since SS* went low).
2. For each bit, starting with the MSB, perform the following action:
Establish the desired SERDATIN level corresponding to this bit.
SERCLK = 0.
SERCLK = 1. This rising edge clocks the data.
These bits are the address of the register of interest.
3. Pull DAQD*/A low to deselect the Address Handler and select the register whose address
was written to the Address Handler. This selects a register for writing to or reading from.
Figure 2-9 illustrates a write to the SCXI-1162 Address Handler of the binary pattern:
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
This pattern is the address of the Data Register.
SERDATIN
SERCLK
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
DAQD*/A
Tdelay
Tdelay SERCLK last rising edge to DAQD*/A low 425 nsec
Figure 2-9. Address Handler Timing Diagram
After the Address Handler has been written to, an address line of a register has been asserted. At
that stage you can read from the SCXI-1162 Data Register or Module ID Register using the
following protocol. The contents of the Module ID Register are reinitialized by deasserting Slot-
Select or by releasing DAQ D*/A high. After the 32 bits of data are read from the Module ID
Register, further data will be zeros until reinitialization occurs. The Data Register latches in the
digital values at the inputs when it is selected (that is, when D*/A goes low). After the 32 bits of
data are read from the Data Register, further data will be invalid until a new pattern is latched in
by reselecting the Data Register.
