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MYiR-Tech

www.myirtech.com

FZ3 Deep Learning Accelerator Card

Hardware Manual

4.3 PL Unit ........................................................................................................................... 19

4.3.1 MIPI-CSI

............................................................................................................... 19

4.3.2 BT1120

................................................................................................................. 19

4.3.3 Expansion IO

....................................................................................................... 20

4.4 Other interface .............................................................................................................. 21

4.4.1 Power input

.......................................................................................................... 21

4.4.2 RTC bat connector

.............................................................................................. 21

4.4.3 Fan connector

...................................................................................................... 21

4.4.4 CAN

....................................................................................................................... 22

4.4.5 RS485

................................................................................................................... 22

Chapter 5 Mechanical parameters ................................................................................. 23

Appendix 1 Warranty & Technical Support Services .................................................. 24

Содержание FZ3

Страница 1: ...MYiR Tech www myirtech com 1 27 FZ3 Deep Learning Accelerator Card Hardware Manual FZ3 Deep Learning Accelerator Card Hardware Manual Version V1 0 ...

Страница 2: ...MYiR Tech www myirtech com 2 27 FZ3 Deep Learning Accelerator Card Hardware Manual Revision History Version Description Date V1 0 Initial Version 2020 06 23 ...

Страница 3: ... Onboard Resources 9 3 1 Hardware resources 9 3 2 Boot Mode JTAG Mode 10 3 3 DDR4 10 3 4 Storage 10 3 4 1 SPI Flash 10 3 4 2 eMMC 12 3 5 Erthernet 13 3 6 USB 14 3 7 Multi channel programmable clock generator 15 3 8 External watchdog and reset 15 Chapter 4 Hardware Introduction 17 4 1 Interface summary 17 4 2 PS Unit 18 4 2 1 DisplayPort 18 4 2 2 PCIe 1x 18 4 2 3 Erthernet 18 4 2 4 USB3 0 HOST 18 4...

Страница 4: ...ual 4 3 PL Unit 19 4 3 1 MIPI CSI 19 4 3 2 BT1120 19 4 3 3 Expansion IO 20 4 4 Other interface 21 4 4 1 Power input 21 4 4 2 RTC bat connector 21 4 4 3 Fan connector 21 4 4 4 CAN 22 4 4 5 RS485 22 Chapter 5 Mechanical parameters 23 Appendix 1 Warranty Technical Support Services 24 ...

Страница 5: ... MP2 graphics processing unit and 16nm FinFET programmable logic The heterogeneous processing system has high performance low power consumption high expansion and other characteristics and can meet various needs in industrial design At the same time Shenzhen Myir Technology Co Ltd provides a variety of mature hardware solutions provides a wealth of embedded operating system software resources thro...

Страница 6: ...ortex R5 can be used for real time processing applications the Mali 400 MP2 can be used to accelerate graphics processing and the FPGA is fully programmable With the expandable I O ports it can adapt to a variety of application AI development scenarios The main chip of the AI development platform uses Xilinx XCZU3EG SFVC784 devices with a speed grade of 1 MYC CZU3EG SOM is designed to support all ...

Страница 7: ...R3L LPDDR3 with ECC External Static Memory 2x Quad SPI NAND NOR DMA Channels 8 Programmable Logic 4 for PL Peripherals High speed PCIe Gen2 x4 2x USB3 0 SATA 3 1 DisplayPort 4x Tri mode Gigabit Ethernet Regular speed 2xUSB 2 0 2x SD SDIO 2x UART 2x CAN 2 0B 2x I2C 2x SPI 4x 32b GPIO Programmable Logic PL MYC XCZU3EG Logic Equivalent Xilinx Kintex Ultrascale FPGA Programmable Logic Cells 154K Look ...

Страница 8: ...pairs of differential signal BANK 44 PL HD BANK 24Pin 12 pairs of differential signal BANK 64 PL HP BANK 52Pin 26 pairs of differential signal BANK 65 PL HP BANK 52Pin 26 pairs of differential signal BANK 66 PL HP BANK 52Pin 26 pairs of differential signal BANK 500 PS side MIO 00 25 26pin multiplex pin BANK 501 PS side MIO 26 51 26pin multiplex pin BANK 502 PS side MIO 52 77 26pin multiplex pin BA...

Страница 9: ... Hardware resources 2GB 4GB DDR4 SDRAM 64bit 2400Mbps 8GB eMMC 32MB QSPI Gigabit Ethernet RS485 1 CAN 1 Peripheral interface and resources 1 Channel SD MMC interface 1 Channel USB2 0 tyepA 1 Channel USB3 0 typeA 1 Channel RJ45 Ethernet interface 1 Channel Mini Displayport interface 1 Channel PCIe x1 interface 1 system reset key 1 FPGA reset key ...

Страница 10: ...to boot the system from the TF CARD or the QSPI flash For detailed information refer to the table below Name PS_MODE0 PS_MODE1 PS_MODE2 PSMODE3 SW1 M0 M1 M2 JTAG ON ON ON QSPI32 ON OFF ON SD1 OFF ON OFF eMMC ON OFF OFF Table 3 2 PS OFF 1 ON 0 3 3 DDR4 The development Board incorporates four Micron DDR4 memory chips MT40A256M16LY 062E IT F forming a 256M x 64 bit interface with a total of 2GB RAM o...

Страница 11: ...SPI Flash MT25QU256ABA1EW9 0SI T Connect to the QSPI0 interface of the CPU PS_MIO0 PSMIO5 pins of BANK500 U12 PS_MIO0 QSPI_LOWER_SCK PS_MIO1 QSPI_LOWER_D1 PS_MIO2 QSPI_LOWER_D2 PS_MIO3 QSPI_LOWER_D3 PS_MIO4 QSPI_LOWER_D0 PS_MIO5 QSPI_LOWER_CS Table 3 4 1 It can be used to initialize the PS subsystem and configure the PL subsystem bitstream ...

Страница 12: ...8GAKAJCN 4M IT 8 bit interface Connectted to CPU SDIO1 PS_MIO13 PS_MIO23 pins of BANK500 U31 PS_MIO13 SD0_EMMC_D0 PS_MIO14 SD0_EMMC_D1 PS_MIO15 SD0_EMMC_D2 PS_MIO16 SD0_EMMC_D3 PS_MIO17 SD0_EMMC_D4 PS_MIO18 SD0_EMMC_D5 PS_MIO19 SD0_EMMC_D6 PS_MIO20 SD0_EMMC_D7 PS_MIO21 SD0_EMMC_CMD PS_MIO22 SD0_EMMC_CLK PS_MIO23 SD0_EMMC_RST Table 3 4 2 ...

Страница 13: ...1B R as the PHY and uses the PS RGMII interface to connect a Gigabit Ethernet mouth The IIC address of PHY is 0x4 AR8035 AL1B R is connected to the PS_MIO64 PS_MIO77 pins of the CPU s ETH0 BANK501 U34 PS_MIO64 ENET_TXC PS_MIO65 ENET_TD0 PS_MIO66 ENET_TD1 PS_MIO67 ENET_TD2 PS_MIO68 ENET_TD3 PS_MIO69 ENET_TX_CTL PS_MIO70 ENET_RXC PS_MIO71 ENET_RD0 PS_MIO72 ENET_RD1 PS_MIO73 ENET_RD2 PS_MIO74 ENET_RD...

Страница 14: ...rt signals is combined with the PS 3 0 USB port Together form a USB3 0 port and several other ports are led out as separate USB2 0 ports USB3320C is connected to the PS_MIO52 PS_MIO63 pins of the USB0 BANK501 of the CPU U35 PS_MIO52 USB0_CLK_IN PS_MIO53 USB0_DIR PS_MIO54 USB0_TX_D2 PS_MIO55 USB0_NXT PS_MIO56 USB0_TX_D0 PS_MIO57 USB0_TX_D1 PS_MIO58 USB0_STP PS_MIO59 USB0_TX_D3 PS_MIO60 USB0_TX_D4 P...

Страница 15: ... clock IC generates the necessary clock for the entire system through external 26 MHz crystal oscillator after frequency multiplication and frequency division processing The schematic diagram is as follows Figure 3 7 1 3 8 External watchdog and reset Figure 3 8 1 The development platform uses an external watchdog chip TPS3828 33DBVT The dog feed pin of this chip is connected to the PS_MIO41 pin of...

Страница 16: ...MIO41 to high impedance during the debugging phase Watchdog work is prohibited The TPS3828 33DBVT also has the function of monitoring the voltage reset system When the power supply voltage reaches the threshold voltage the reset automatically pulls up to start the system The reset signal is connected to ZU3EG which can directly reset the main chip ...

Страница 17: ...Interface summary Figure 4 1 Num Description J1 Power input 12V 2A J6 DisplayPort PS J8 Gigabyte Erthnet PS J2 1xUSB3 0 1xUSB2 0 PS J5 PCIe x1 PS J12 TF Card PS J3 BT1120 video input PL J4 MIPI CSI image input PL J13 JTAG J11 MicroUSB to UART debug port PS J9 Bat connector J10 Fan connector J15 J16 Expansion IO Table 4 1 ...

Страница 18: ...0 100 1000Mbps Ethernet RJ45 interface the port is J8 4 2 4 USB3 0 HOST One USB 2 0 interface up 1 USB3 0 interface down led out through the double layer USB3 0 TYPE A interface on the board as HOST the interface is J2 4 2 5 TF Card One TF card slot used for boot or storage the interface is J12 4 2 6 MicroUSB to UART One MicroUSB to UART interface for debugging the interface is J11 4 2 7 JTAG One ...

Страница 19: ...ugh the IO on the PL end and enters the FPGA for decoding For detailed IO details please refer to the PINMAP Interface bit J4 Figure 4 3 1 4 3 2 BT1120 This development board has a BT1120 video input interface on the PL end The BT1120 video signal directly passes through the IO on the PL end and enters the FPGA to be decoded by unique logic For detailes about the IO please refer to the PINMAP the ...

Страница 20: ...54 pin headers for IO expansion including 12V 5V 3 3V 1 8V and other power output CAN RS485 USB2 0x2 4xPSMIO 40PIN PL terminal IO and other signals The interfaces are J15 and J16 For the detailed signal definition and details please refer to the schematic diagram and the ROUTE length form The applicable connector specifications are in the CD ROM Figure 4 3 2 ...

Страница 21: ...current protection is 2A It is recommended to use 12V 2A power input The interface is J1 4 4 2 RTC bat connector This development board has left RTC battery interface can use 1 5V AG3 LR41 type battery the interface is J9 4 4 3 Fan connector This development board has a fan interface which is powered by 12V by default The fan speed can be detected through the PL terminal IO The interface is J10 Fi...

Страница 22: ...e drawn from pins 14 and 16 of interface J16 Figure 4 4 4 4 4 5 RS485 This development board has an RS485 interface and signals are drawn from pins 8 and 10 of interface J16 Figure 4 4 5 CAUTION For the specific access pins of the signal please refer to the PINMAP table in the CD There are detailed definitions and related trace length data ...

Страница 23: ...er 5 Mechanical parameters Operating Temperature 40 85 Industrial grade default 0 70 Commercial grade Humidity 20 90 Power Supply 12V Limited support 6V 12 6V Expansion IO Two 40pin 2 54 spacing dip connector PCB 12 Layer Immersion Gold Lead free Dimensions PCB 100mm x 70mm FAN 60mm x 52mm ...

Страница 24: ...o customers the warranty and technical support services provided by MYIR as well as the matters needing attention in using MYIR s products Service Guarantee MYIR regards the product quality as the life of an enterprise We strictly check and control the core board design the procurement of components production control product testing packaging shipping and other aspects and strive to provide produ...

Страница 25: ...un the source code we offer c To help customers solve problems occurred during operations if users follow the user manual documents d To judge whether the failure exists e To provide free software upgrading service However the following situations are not included in the scope of our free technical support service a Hardware or software problems occurred during customers own development b Problems...

Страница 26: ...y customer should contact MYIR within 7 business days from the moment get the goods 2 Please do not use finger nails or hard sharp object to touch the surface of the LCD 3 MYIR suggests user purchasing a piece of special wiper to wipe the LCD after long time use please avoid clean the surface with fingers or hands to leave fingerprint 4 Do not clean the surface of the screen with chemicals 5 Pleas...

Страница 27: ...rs 5 Products Life Cycle MYIR will always select mainstream chips for our design thus to ensure at least ten years continuous supply if meeting some main chip stopping production we will inform customers in time and assist customers with products updating and upgrading Value added Services 1 MYIR provides services of driver development base on MYIR s products like serial port USB Ethernet LCD etc ...

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