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FZ3 Deep Learning Accelerator Card
Hardware Manual
3.7
Multi-channel programmable clock generator
This development platform has a programmable IDT SI5332 I2C programmable clock
generator. This clock IC generates the necessary clock for the entire system through
external 26 MHz crystal oscillator after frequency multiplication and frequency division
processing. The schematic diagram is as follows:
Figure 3-7-1
3.8 External watchdog and reset
Figure 3-8-1
The development platform uses an external watchdog chip TPS3828-33DBVT. The dog
feed pin of this chip is connected to the PS_MIO41 pin of the CPU. When PS_MIO41 is
