Multitone RPR 563GS, Техническое руководство

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RPR 563GS/KGS
TM1187A Issue C Page 5 - 22
PIN NAME DESCRIPTION
1 OSEN Oscillator cell enable
3 CLK Clock input: 512 baud = 32.768kHz, 1200 baud = 38.400kHz
5 RESB Reset input: 0 = reset
7 DIN Data input
9 BEC Radio enable: 0 = radio on, 1 = radio off
10 VDD1 Low voltage supply rail (0.9V - 1.5V)
11 VSS Ground
13 TON Beep drive: 0 = transducer on, 1 = transducer off
15 VIB Vibrate motor drive: 0 = motor on, 1 = motor off
17 OFF VDD enable: 0 = VDD on, 1 = VDD off
19 RSO Reset out: 0 = µP enabled, 1 = µP reset
21 LP2 LED enable
22 VSS Ground
25 CS Chip select: 0 = chip selected, 1 = chip deselected
26 E Data transfer clock: = data transfer
27 RW Read/Write: 0 = write to chip, 1 = read from chip
28 RS Register select: 0 = data register, 1 = address/status
30 VSS Ground
31 VDD2 µP supply rail
35 DA0
Tri-state bi-directional buffer: bi-directional data bus
DA3 = most significant bit
DA0 = least significant bit
36 DA1
37 DA2
38 DA3
39 VSS Ground
42 TSF 128Hz output
50 VSS Ground
51 VDD1 Low voltage supply rail (0.9V - 1.5V)
53 ON On enable: 0 = switch on, 1 = quiescent mode
55 S1I `On'
Switch inputs: 0 = switch closed, 1 = switch open 57 S2I `Off'
59 S3I `Mute'
62 VSS Ground
63 S10
Tri-state, switch outputs: 0 = switch closed, Z = switch open
(Z = high impedance output)
64 S20
65 S30
66 DTI Tri-state, data interrupt: = data interrupt
67 SWI Tri-state, switch output: = switch operation
68 TMI Tri-state, timer interrupt: = 2s elapsed
70 VSS Ground
71 VDD2 µP supply rail
72 SYN Tri-state, sync word detected: 0 = sync word present in data register
76 SCK Tri-state, sample clock: = sample point of data bit
77 VSS Ground
78 QIN VDD
79 VSS Ground
NOTE: Z = high impedance output. = falling edge of output signal.
Table 6: Gate Array (IC105) Pin Connections