BIOS Setup
4-13
Note:
Change these settings only if you are familiar with the chipset.
Advanced Chipset Features
DRAM Timing Setting
Press <Enter> and the following sub-menu appears.
Configure DRAM Timing by SPD
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to
Enabled
enables
CAS# Latency, RAS# Precharge, RAS# to CAS# Delay, Precharge Delay
and Burst Length automatically to be determined by BIOS based on the
configurations on the SPD. Selecting
Disabled
allows users to configure
these fields manually.