MSC Technologies Avnet COM Express CXC-BT, Руководство пользователя

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MSC CXC-BT User Manual
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2.10.9
LPC Bus
Signal Pin
Type Signal
Level Power Rail Remark /
Tolerance PU/PD/SR Description Source / Target
LPC_AD[0:3] I/O CMOS 3.3V 3.3V LPC multiplexed address, command and data bus BT SOC
LPC_FRAME# O CMOS 3.3V LPC frame indicates the start of an LPC cycle BT SOC
LPC_DRQ0# I CMOS 3.3V 3.3V LPC serial DMA request not connected
LPC_DRQ1# I CMOS 3.3V LPC serial DMA request not connected
LPC_SERIRQ I/OD CMOS 3.3V 3.3V LPC serial interrupt BT SOC
LPC_CLK O CMOS 3.3V eSR = 10
Ω LPC clock output - 33MHz nominal, functional strap option BT SOC
Note: For signal buffering to external devices a zero delay buffer is needed.
LPC_CLK is running in continuous mode.
2.10.10
LVDS Flat Panel
Signal Pin
Type Signal
Level Power
Rail Remark /
Tolerance PU/PD/SR Description Source / Target
LVDS_A[0:3]+
LVDS_A[0:3]- O LVDS LVDS Channel A differential pairs ANX1122
LV
LVDS_A_CK- O LVDS LVDS Channel A differential clock ANX1122
LVDS_B[0:3]+
LVDS_B[0:3]- O LVDS LVDS Channel B differential pairs ANX1122
LV
LVDS_B_CK- O LVDS LVDS Channel B differential clock ANX1122
LVDS_VDD_EN O CMOS 3.3V LVDS panel power enable ANX1122
LVDS_BKLT_EN O CMOS 3.3V LVDS panel backlight enable Embedded
Controller
LVDS_BKLT_CTRL O CMOS 3.3V eSR =47.5
Ω
LVDS panel backlight brightness control Embedded
Controller
LVDS_I2C_CK O CMOS 3.3V ePU = 2.2 K
Ω
ePD = 100
KΩ
I2C clock output for LVDS display use
(100k ePD is required for eDP) ANX1122
LVDS_I2C_DAT I/OD CMOS 3.3V 3.3V ePU = 2.2 K
Ω
ePU = 100
KΩ
I2C data line for LVDS display use
(100k ePU is required for eDP) ANX1122