Controller Circuits
Section 3: 1-5
1.6
Mechanical ON/OFF
This refers to the typical On/Off/Volume knob, located on the control head, and which turns the radio
on and off.
If the radio is turned off and the On/Off/Volume knob is pressed, line ON OFF CONTROL (J0401 pin
11) goes high and switches the radio’s voltage regulators on as long as the button is pressed. The
µP is alerted through line ON OFF SENSE (U0101 pin 6) which is pulled to low by Q0110 while the
On/Off/Volume knob is pressed. In addition, an interrupt is generated at µP pin 96. The µP asserts
line DC POWER ON via ASFIC CMP, pin 13 high which keeps Q0661 and Q0641, and in turn the
radio, switched on. When the On/Off/Volume knob is released again the control head informs the µP
via SBEP bus about the knob release. (See SBEP Serial Interface subsection for more details.) This
informs the µP to keep the radio switched on and continue with normal operation.
If the On/Off/Volume knob is pressed while the radio is on, the control head informs the µP via
SBEP bus about the knob status. (See SBEP Serial Interface subsection for more details.) After a
short delay time the µP switches the radio off by setting DC POWER ON to low via ASFIC CMP pin
13.
1.7
Ignition
Ignition sense is used to prevent the radio from draining the vehicle’s battery because the engine is
not running.
When the IGNITION input (J0501 pin 10) goes above 5 volts Q0661 is turned on via line IGNITION
CONTROL. Q0661 turns on INT SW B+ and the voltage regulators by turning on Q0641 and the µP
starts execution. The µP is alerted through line GP6 IN ACC10. The voltage at the IGNITION input
turns Q0181 on, which pulls µP pin 74 to low. If the software detects a low state it asserts DC
POWER ON via ASFIC pin 13 high which keeps Q0661 and Q0641 on, and in turn the radio
switched on.
When the IGNITION input goes below 3 volts, Q0181 switches off and R0181 pulls µP pin 74 to
high. This alerts the software to switch off the radio by setting DC POWER ON to low. The next time
the IGNITION input goes above 5 volts the above process will be repeated.
1.8
Microprocessor Clock Synthesizer
The clock source for the µP system is generated by the ASFIC CMP (U0221). Upon power-up the
synthesizer IC (FRAC-N) generates a 16.8 MHz waveform that is routed from the RF section to the
ASFIC CMP pin 34. For the main board controller the ASFIC CMP uses 16.8 MHz as a reference
input clock signal for its internal synthesizer. The ASFIC CMP, in addition to audio circuitry, has a
programmable synthesizer which can generate a synthesized signal ranging from 1200 Hz to
32.769 MHz in 1200 Hz steps.
When power is first applied, the ASFIC CMP will generate its default 3.6864 MHz CMOS square
wave UP CLK (on U0221 pin 28) and this is routed to the µP (U0101 pin 90). After the µP starts
operation, it reprograms the ASFIC CMP clock synthesizer to a higher UP CLK frequency (usually
7.3728 or 14.7456 MHz) and continues operation.
The ASFIC CMP may be reprogrammed to change the clock synthesizer frequencies at various
times depending on the software features that are executing. In addition, the clock frequency of the
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