Motorola PRO Series, Подробное руководство по обслуживанию

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Low Band Transmitter Power Amplifier (PA) 60 W Section 7: 2-5
6881091C63-F
3.2 Driver Stage
The next stage is an LDMOS device (Q1401) providing a gain of 13 dB. This device requires a
positive gate bias and a quiescent current flow for proper operation. The voltage of the line
MOSBIAS_1 is set during transmit mode by the PCIC pin 24, and fed to the gate of Q1401 via
resistors R1402, R1447, R1449, R1458, R1459, and R1463. The bias voltage is tuned in the factory.
The circuitry associated with U1402-2 and Q1404 limits the variation in the output power of the
driver stage resulting from changes in the input impedance of the final stage due to changes at the
antenna of the radio. The variation in the driver’s output power is limited by controlling its DC
current. The driver’s DC current is monitored by measuring the voltage drop across current-sense
resistors R1473-6, and this voltage is compared to a reference voltage on pin 6 of U1402-2. If the
current through the sense resistors decreases, the circuit increases the bias voltage on the gate of
Q1401 via Q1404. If the current increases, then the bias voltage decreases in order to keep the
driver’s current constant. Since the current must increase with increasing control voltage, an input
path is provided to U1402-2 pin 5 from control line VCNTRL to enable this.
3.3 Final Stage
The final stage uses two LDMOS FET devices operating in parallel. Each device has its own
adjustable gate bias voltage, MOSBIAS_2 and MOSBIAS_3, obtained from D/A outputs of the
ASFIC. These bias voltages are also factory-tuned. If these transistors are replaced, the bias
voltage must be tuned using the Tuner software. Care must be taken not to damage the device by
exceeding the maximum allowed bias current. The device’s drain current is drawn directly from the
radio’s DC supply voltage input, PASUPVLTG, via current-measurement resistor R1409.
A matching network combines the output of the two devices and provides a 50-ohm source for the
antenna switch and harmonic filter.
3.4 Antenna Switch
The antenna switch is operated by the 9T1 voltage source which forward biases diodes D1401 and
D1402 during transmit, causing them to appear as low impedance. D1401 allows the RF output from
final stages Q1402 and Q1403 to be applied to the input of the low-pass harmonic filter (L1421-3
and associated components). D1402 appears as a short circuit at the input of the receiver (RXINJ),
preventing transmitter RF power from entering the receiver. L1420 and C1456 appear as a
broadband-wave transmission line, making the short circuit presented by D1402 appear as an open
circuit at the junction of D1401 and the harmonic filter input.
During receive mode, the 9T1 voltage is not present, and D1401 and D1402 do not conduct and
appear as open circuits. This allows signals from the antenna jack to pass to the receiver input, and
disconnects the transmitter final stages from this path.
3.5 Harmonic Filter
Components L1421- L1423 and C1449-C1455 form a seven-pole elliptic low-pass filter to attenuate
harmonic energy of the transmitter to specifications level. R1411 is used to drain electrostatic
charge that might otherwise build up on the antenna. The harmonic filter also prevents high level RF
signals above the receiver passband from reaching the receiver circuits, improving spurious
response rejection.