Memory Maps
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2-7
2
For detailed processor memory maps, including suggested CHRP- and
PREP-compatible memory maps, refer to the MVME2600 Series Single
Board Computer Programmer’s Reference Guide, listed in
Appendix D,
Related Documentation
.
PCI Local Bus Memory Map
The PCI memory map is controlled by the Raven MPU/PCI bus bridge
controller ASIC and by the Universe PCI/VME bus bridge ASIC. The
Raven and Universe devices adjust system mapping to suit a given
application via programmable map decoder registers.
No default PCI memory map exists. Resetting the system turns the PCI
map decoders off, and they must be reprogrammed in software for the
intended application.
For detailed PCI memory maps, including suggested CHRP- and PREP-
compatible memory maps, refer to the MVME2600 Series Single Board
Computer Programmer’s Reference Guide, listed in
Appendix D, Related
Documentation
.
VMEbus Memory Map
The VMEbus is programmable. Like other parts of the MVME2603/2604
memory map, the mapping of local resources as viewed by VMEbus
masters varies among applications.
The Universe PCI/VME bus bridge ASIC includes a user-programmable
map decoder for the VMEbus-to-local-bus interface. The address
translation capabilities of the Universe enable the processor to access any
range of addresses on the VMEbus.
Recommendations for VMEbus mapping, including suggested CHRP- and
PREP-compatible memory maps, can be found in the MVME2600 Series
Single Board Computer Programmer’s Reference Guide, listed in
Appendix D, Related Documentation
.
Figure 2-2 on page 2-9
shows the
overall mapping approach from the standpoint of a VMEbus master.
