Motorola MPC505EVB, Руководство пользователя, Страница: 57 / 58

SUPPORT INFORMATION
MPC505EVBUM/D 4-15
Table 4-15. Logic Analyzer Connector POD7 Pin Assignments
Pin Mnemonic Signal
1, 2 NC Not Connected
3 CLKOUT SYSTEM CLOCK OUT – Output signal that is the MPC505 MCU
internal system clock.
4 BURST BURST – Active low indicates a burst cycle.
5 TEA* TRANSFER ERROR ACKNOWLEDGE – An active-low input signal that
indicates bus error condition.
6 AACK* ADDRESS ACKNOWLEDGE – An active-low input signal that indicates
the slave has received the address from the bus master.
7 TA* TRANSFER ACKNOWLEDGE – An active-low input signal that
indicates the slave has received data during a write cycle or returned
data during a read cycle.
8 – 11 BE0* – BE3* BYTE ENABLE (0 3) Active-low output signals where one byte enable
controls one byte lane of the data bus.
12 BDIP* BURST DATA IN PROGRESS – An active-low output signal that
indicates the data beat in front of the current one is needed by the
master.
13 R_W* READ/WRITE – Active-high output signal that indicates the direction of
data transfer on the bus.
14 TS* TRANSFER START – An active-low output signal that indicates the
start of a bus cycle.
15, 16 AT0, AT1 ADDRESS TYPES (0 & 1) – One of two output bits that defines address
space as: user data, user instruction, supervisor data, or supervisor
instruction.
17 BI* BURST INHIBIT – Active-low input signal that indicates the slave does
not support burst mode.
18 ARETRY* ADDRESS PHASE RETRY – An active-low input signal that indicates
the master needs to retry its address phase.
19 CSBT* BOOT CHIP SELECT – Active-low output signal that selects peripheral
or memory devices at programmed addresses.
20 GND GROUND