Motorola MPC505EVB, Руководство пользователя, Страница: 56 / 58

SUPPORT INFORMATION
4- 14 MPC505EVBUM/D
Table 4-14. Logic Analyzer Connector POD6 Pin Assignments
Pin Mnemonic Signal
1 – 3 NC Not Connected
4 CLKOUT SYSTEM CLOCK OUT – Output signal that is the MPC505 MCU
internal system clock.
5 RESET* RESET – Active-low, input signal that resets the MPC505 MCU.
6 SRESET* SYSTEM RESET – Active-low, MPC505 MCU output signal that resets
the EVB.
7 – 10 CT0 – CT3 CYCLE TYPE SIGNALS – Four bits that indicate what type of bus cycle
the bus master is initiating.
11 CR* CANCEL RESERVATION Active-low input that instructs the bus master
to clear the external device's reservation.
12 BR* BUS REQUEST – Active-low input signal that indicates that an external
device requests bus mastership.
13 BB* BUS BUSY – Active-low, bi-directional signal asserted by the current
master that indicates that the bus is in use.
14 BG* BUS GRANT – Active-low input signal that indicates that an external
device has assumed control of the bus.
15, 16 IRQ0*, IRQ1* INTERRUPT REQUEST (0, 1) – Prioritized active low input lines that
requests MCU synchronous interrupts. IRQ1* has the highest priority.
17 ECROUT ENGINEERING CLOCK REFERENCE OUT Clock reference for
peripheral chips.
18 MODCLK CLOCK MODE SELECT – Active-high input signal that selects the
source of the internal system clock.
19 PDWU POWER DOWN WAKEUP Output signal sends a power-down wakeup
to external power-on reset circuits.
20 GND GROUND