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SUPPORT INFORMATION

4-

4

MPC505EVBUM/D

Table 4-2. RS-232C I/O Connector P2 Pin Assignments

Pin

Mnemonic

Signal

1

ADCD*

DATA CARRIER DETECT – An output signal used to indicate an
acceptable received line (carrier) signal has been detected.

2

ARXD

RECEIVE DATA – RS-232C serial input signal.

3

ATXD

TRANSMIT – RS-232C serial output signal.

4

ADTR*

DATA TERMINAL READY – An output line that indicates an on-line/in-
service/active status.

5

GND

GROUND

6

ADSR*

DATA SET READY – An output signal (held high) that indicates an on-
line/in-service/active status.

7

ARTS

REQUEST TO SEND – An input signal used to request permission to
transfer data.

8

ACTS*

CLEAR TO SEND – An output signal that indicates a ready-to-transfer
data status.

9

NC

Not Connected

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Содержание MPC505EVB

Страница 1: ...MPC505EVB D March 1997 MPC505EVB EVALUATION BOARD USER S MANUAL MOTOROLA Inc 1994 All Rights Reserved ...

Страница 2: ...re personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or d...

Страница 3: ...der J4 2 7 2 2 5 Burst Memory Select Header J5 2 7 2 2 6 System Clock Selection Headers J6 and J7 2 8 2 2 7 EVB LED Descriptions 2 9 2 2 8 Optional Memory Configuration 2 9 2 2 9 EVB Reset Switches 2 10 2 2 10 EVB DIP Switches 2 10 2 2 10 1 Chip Select Dip Switch DS1 2 11 2 3 10 2 Reset Data Dip Switches DS2 DS5 2 12 2 2 10 3 DTE DCE Settings 2 15 2 3 INSTALLATION INSTRUCTIONS 2 16 2 3 1 Host Comp...

Страница 4: ...NNECTORS 3 7 3 5 1 64 Pin Expansion Connectors 3 7 3 5 2 Serial Communication Connectors 3 7 3 5 3 Background Mode Interface Connector 3 7 3 6 PFB DESCRIPTION 3 7 3 6 1 Floating Point Coprocessor Socket U5 3 7 3 6 2 Logic Analyzer Connectors 3 8 CHAPTER 4 SUPPORT INFORMATION 4 1 INTRODUCTION 4 1 4 2 CONNECTOR SIGNAL DESCRIPTIONS 4 1 FIGURES 2 1 EVB Connector Switch and Jumper Header Location Diagr...

Страница 5: ...nector P2 Pin Assignments 4 4 4 3 RS 232C I O Connector P3 Pin Assignments 4 5 4 4 Host Computer Connector P4 Pin Assignments 4 6 4 5 Debug Mode Connector P5 Pin Assignments 4 7 4 6 P6 Expansion Connector Pin Assignments 4 8 4 7 Input Power Connector P7 Pin Assignments 4 9 4 8 P8 Expansion Connector Pin Assignments 4 9 4 9 Logic Analyzer Connector POD1 Pin Assignments 4 12 4 10 Logic Analyzer Conn...

Страница 6: ...CONTENTS vi MPC505EVB D PRELIMINARY ...

Страница 7: ...2 kilobytes of flash memory may be upgraded to 2 megabytes 128 kilobytes of synchronous static RAM may be upgraded to 1 megabyte Serial port with 25 pin RS 232 connector to host computer MC68681 DUART providing two serial interfaces for RS 232 evaluation MC68HC711 MCU for the background debug mode port interface SCSI 2 port optional Expansion connectors for the MPC505 MCU signals 20 pin logic anal...

Страница 8: ...ou evaluate MPC505 control of RS 232 communication These ports can be configured as either data computer equipment DCE or data terminal equipment DTE protocol via a set of switches An example of DCE is a modem and DTE a computer terminal These serial ports are available to you at all times the development system monitor MPCbug does not require these ports Supported baud rates for P2 and P3 are 120...

Страница 9: ...h larger devices Alternately you may increase the amount of on board SSRAM by populating U20 U21 U22 U30 U31 and U32 with additional SSRAM devices You may increase the SSRAM size up to 1 megabytes For information on increasing on board memory see paragraph 2 2 9 The EVB includes an optional SCSI 2 port connection on the MPC505 The required parts are not provided and the user may add them if the SC...

Страница 10: ...PC505EVBUM D 1 5 EQUIPMENT REQUIRED Table 1 2 lists the external equipment requirements for EVB operation Table 1 2 External Equipment Requirements External Equipment 5 Vdc power supply SUN host computer RS 232C cable assembly ...

Страница 11: ...itches DS2 through DS5 define the data bus reset configuration word Dip switch DS6 sets P2 P3 P4 and for BDM connector as DTE or DCE Jumper headers J1 through J7 are for customizing EVB operation described in Table 2 2 and paragraphs 2 2 1 through 2 2 5 Connector P1 is a SCSI interface connector not populated Connectors P2 and P3 let you connect RS 232C devices to the EVB for evaluation purposes C...

Страница 12: ...HARDWARE PREPARATION AND INSTALLATION 2 2 MPC505EVBUM D Figure 2 1 EVB Connector Switch and Jumper Header Location Diagram ...

Страница 13: ...ber To change the factory jumper header configuration move the jumper to the two desired pins Table 2 2 MPFB Jumper Header Descriptions Jumper Header Type Description J1 Crystal clock sourcr select header XTAL 2 1 Bus wire soldered between pins 1 and 2 factory default selects the EVB on board 4 MHz crystal clock source Bus wire between pins 1 and 2 is removed lets you select an external clock sour...

Страница 14: ...PWR2 pin of the MCU 3 3 Vdc external power supply attached to jumper header J4 pins 2 and 3 maintains MCU internal oscillator time base and decrementer operates after EVB power is turned OFF J5 Unused J6 System clock selection header 3 2 1 Jumper installed on pins 1 and 2 factory default jumper headers J6 and J7 select the MCU clock mode The state of this signal during reset selects the source of ...

Страница 15: ... crystal clock circuit is 4 MHz The frequency of the crystal oscillator circuit can be as fast as 40 MHz J1 2 1 Bus Wire The EVB comes with a 4 MHz crystal and a socket for a crystal oscillator The EVB is factory configured to use the 4 MHz crystal as the input You can configure the clock frequency up to 33 MHz by setting the MF bits bits 9 12 and RFD bits bits 28 31 in register SCCR at address 0x...

Страница 16: ...it is 4 MHz The frequency of the crystal oscillator circuit can be as fast as 40 MHz J2 3 2 1 Bus Wire 2 2 3 Keep Alive Power 2 Select Header J3 Jumper header J3 provides power to the MCU internal RAM module via the MCU VKAPWR2 pin You may use either the on board 3 3 Vdc jumper on J3 pins 1 and 2 or connect an external 3 3 Vdc power supply to J3 pins 2 and 3 An external 3 3 Vdc power supply on J3 ...

Страница 17: ...c power supply on J4 pins 2 and 3 will maintain MCU internal RAM data after EVB power is turned OFF To attach an external power supply to VKAPWR1 remove the jumper on J4 pins 1 and 2 and connect the power supply ground to J4 pin 3 and 3 3 Vdc to pin 2 CAUTION Applying power to the EVB with J4 removed and no external power supply attached to J4 will damage the MPC505 MCU Always keep a jumper or an ...

Страница 18: ... operation a fabricated jumper on J6 and J7 pins 1 and 2 Refer to Table 2 4 for configuring the system clock source Table 2 4 System Clock Source Configuration MODCLK J6 Jumper Settings VDDSYN J7 Jumper Settings System Phase Lock Loop Options 1 and 2 default 1 and 2 default Normal Operation 2 and 3 1 and 2 1 1 Mode 1 and 2 2 and 3 SPLL Bypass Mode 2 and 3 2 and 3 Special Test Mode J7 3 2 1 Fabrica...

Страница 19: ...transfers Each pair is refered to as BANKx Table 2 5 shows on board memory configuration options Table 2 5 Optional Memory Configuration Bank Upper Word Lower Word 64Kb Memory Part Numbers 128Kb Memory Part Numbers BANK1 U29 U19 MCM67M518 MCM67M618 BANK2 U30 U20 MCM67M518 MCM67M618 BANK3 U31 U21 MCM67M518 MCM67M618 BANK4 U32 U22 MCM67M518 MCM67M618 The SSRAM factory default for the EVB is 128 kilo...

Страница 20: ...the EVB on board memory and peripheral devices You may disable on board chip selects and connect them via the expansion connectors P6 and P8 to external memory or peripheral devices DS2 DS3 DS4 DS5 Data Bus Reset Configuration Word DS6 On the EVB are 3 RS232 ports P2 P3 P4 and one background debug mode connector P5 Each of the RS 232 ports can be either DTE or DCE port defined by DS6 switches 2 3 ...

Страница 21: ...nsion connectors To avoid conflicts between on board and external devices disable the appropriate chip select by setting the appropriate DS1 switch see Table 2 6 Table 2 6 Chip Select Dip Switch DS1 Pin Chip Select Device Connected to Chip Select 1 CSBOOT Flash chip select U24 U25 U27 U28 2 FOE Flash output enable U24 U25 U27 U28 3 CS1 Burst RAM Bank1 U19 U29 4 CS2 Burst RAM Bank2 U20 U30 5 CS3 Bu...

Страница 22: ...ation on the internal reset configuration mode refer to the PowerPC MPC505 RISC Microcontroller Technical Summary MPC505TS D Table 2 7 Data Bus Reset Configuration Word Data Bus Bit Configuration Function Effected Effect of Mode Select 1 During Reset Effect of Mode Select 0 During Reset EVB Default Mode 0 Address Bus Minimum Bus Mode ADDR 0 11 CS 0 11 Maximum Bus Mode ADDR 0 11 Address Pins 1 1 Ve...

Страница 23: ... source for DATA 14 21 Latch configuration from external pins Latch configuration from internal defaults 1 14 CT 0 3 AT 0 1 TS CT 0 3 AT 0 1 TS PJ 1 7 1 15 WR BDIP WR BDIP PK 0 1 0 16 PLLL DSDO VF 0 2 VFLS 0 1 WP 1 5 DSDO Pipe Tracking Watchpoints PK 2 7 PL 2 7 1 17 BURST TEA AACK TA BE 0 3 Handshake Pins PORTI 0 7 1 18 CR BI BR BB BG ARETRY Bus Arbitration Pins PM 2 7 1 19 Release reset when PLL ...

Страница 24: ...fault Mode 24 LEN L bus Memory modules are enabled L bus Memory modules are disabled and emulated externally 1 25 PRUMODE Forces accesses to Ports A B I J K and L to go external No effect 0 26 ADDR 12 15 ADDR 12 15 PB 4 7 1 27 Reserved 0 28 Reserved 0 29 Reserved 0 30 Test Slave Mode Enable Test Slave Mode Disabled Test Slave Mode Enabled 1 31 Test Transparent Mode Enable Test Transparent Mode Dis...

Страница 25: ...connectors P2 P3 and P4 as DTE or DCE Table 2 8 shows DS6 switch settings Table 2 8 DS6 Communication Type Switch Settings Pin Signal Name Connector Description 1 OEDSDIDSCK P4 P5 Switch to ON when using P4 as the I O port Switch to OFF when using BDM connector P5 as the I O port 2 ADCE_DTE P2 ON DTE OFF DCE 3 BDCE_DTE P3 ON DTE OFF DCE 4 CDCE_DTE P4 ON DTE OFF DCE 5 UNUSED 6 UNUSED 7 UNUSED 8 UNU...

Страница 26: ...r to the EVB is accomplished via a user supplied 25 pin flat cable assembly One end of the cable assembly is connected to the EVB connector P4 shown below The other end of the cable assembly is connected to the host computer For connector pin assignments and signal descriptions of the EVB I O port connector P4 refer to Appendix B 1 2 3 4 5 6 7 8 9 10 11 12 13 NC CTXD CRXD CRTS CCTS CDSR GND CDCD N...

Страница 27: ...he EVB via the background debug mode BDM You may use the serial development interface SDI as your BDM interface Connect one end of the SDI to your host computer and the other to connector P5 For more information about the SDI refer to the M68SDIUM Users Manual M68SDIUM D P5 VFLS0 1 2 SRESET GND 3 4 DSCK GND 5 6 VFLS1 RESET 7 8 DSDI VCC V3 3 9 10 DSDO ...

Страница 28: ...ion The EVB requires 5 Vdc 2 amp power supply for operation Connector P7 pin 1 is 5 Vdc pins 2 and 3 are ground shown in Figure 2 2 Use 16 22 AWG wire in the connector supplied with the board EVB power supply interconnection for connector P7 is shown below Figure 2 2 Power Supply Connector P7 ...

Страница 29: ...able assembly is connected to either EVB port P2 or P3 shown below The other end of the cable assembly is connected to the user supplied RS 232C compatible device For connector pin assignments and signal descriptions of the EVB RS 232C ports P2 and P3 refer to Appendix B 1 2 3 4 5 ADCD ARXD ATXD ADTR GND P2 RS 232 DEVICE 6 7 8 9 ADSR ARTS ACTS NC 1 2 3 4 5 BDCD BRXD BTXD BDTR GND P3 RS 232 DEVICE ...

Страница 30: ... 6 A24 7 CS3 7 A14 7 A25 8 CS2 8 A15 8 A26 9 CS1 9 A16 9 A27 10 GND 10 A17 10 A28 11 GND 11 A18 11 A29 12 GND 12 A19 12 GND 13 GND 13 A20 13 D16 14 GND 14 GND 14 D17 15 GND 15 D0 15 D18 16 GND 16 D1 16 D19 17 GND 17 D2 17 D20 18 GND 18 D3 18 D21 19 GND 19 D4 19 D22 20 GND 20 D5 20 D23 21 GND 21 D6 21 D24 22 GND 22 D7 22 D25 23 GND 23 D8 23 D26 24 GND 24 D9 24 D27 25 GND 25 D10 25 D28 26 GND 26 D11...

Страница 31: ... GND 12 GND 12 CT3 12 BURST 13 GND 13 GND 13 WP0 14 GND 14 VF0 14 WP1 15 GND 15 VF1 15 WP2 16 GND 16 VF2 16 WP3 17 GND 17 R_W 17 WP4 18 GND 18 TA 18 WP5 19 GND 19 TEA 19 NC 20 GND 20 AT1 20 AT0 21 GND 21 NC 21 ECROUT 22 GND 22 ARETRY 22 BE0 23 GND 23 BG 23 BE1 24 GND 24 BR 24 BE2 25 GND 25 BB 25 BE3 26 GND 26 RESET 26 NC 27 GND 27 SRESET 27 CR 28 GND 28 VFLS1 28 PDWU 29 GND 29 VFLS0 29 NC 30 VCC 3...

Страница 32: ... 4 A16 CS1 5 6 CS2 A17 5 6 A18 CS3 7 8 CS4 A19 7 8 A20 CS5 9 10 BSWE0 A21 9 10 A22 BSWE1 11 12 BSWE2 A23 11 12 A24 BSWE3 13 14 A10 A25 13 14 A26 A11 15 16 A12 A27 15 16 A28 A13 17 18 A14 A29 17 18 GND A30 A15 19 20 GND A31 GND 19 20 GND POD3 POD4 NC 1 2 NC NC 1 2 NC NC 3 4 D16 NC 3 4 D0 D17 5 6 D18 D1 5 6 D2 D19 7 8 D20 D3 7 8 D4 D21 9 10 D22 D5 9 10 D6 D23 11 12 D24 D7 11 12 D8 D25 13 14 D26 D9 1...

Страница 33: ...D PDWU 19 20 GND POD7 NC 1 2 NC CLKOUT 3 4 BURST TEA 5 6 AACK TA 7 8 BE0 BE1 9 10 BE2 BE3 11 12 BDIP R_W 13 14 TS AT0 15 16 AT1 BI 17 18 ARETRY CSBT 19 20 GND 2 3 7 SCSI The EVB printed circuit board includes an optional SCSI port The required parts for the SCSI port are user supplied SCSI port parts list is provided in Table 2 9 Table 2 9 SCSI Port Parts List Reference Designation Component Descr...

Страница 34: ...HARDWARE PREPARATION AND INSTALLATION 2 24 MPC505EVBUM D ...

Страница 35: ...the PFB you may evaluate the MCU and debug user developed code To do this connect a terminal or host computer to PFB connector P9 and run the MPCbug debug monitor program Logic analyzer connection may be made to connectors P1 through P6 of the PFB Mount the BCC on the target system to verify hardware design With the BCC mounted on the target system MC68332 MCU device emulation with hardware breakp...

Страница 36: ...FUNCTIONAL DESCRIPTION 3 2 MPC505EVBUM D Figure 3 1 EVB Block Diagram ...

Страница 37: ...andom access memory RAM External bus interface Chip selects System clock Test module 3 3 1 32 Bit Central Processor Unit The CPU32 is the central processor for the MC68332 MCU device The CPU32 is source and object code compatible with the MC68000 and MC68010 All user programs can be executed unchanged The CPU32 features are 32 Bit internal data path and arithmetic hardware 16 bit external data bus...

Страница 38: ...ble peripheral select pins provide address ability for as many as 16 peripheral devices A QSPI enhancement is an added queue in a small RAM This lets the QSPI handle as many as 16 serial transfers of 8 to 16 bits each or to transmit a stream of data as long as 256 bits without CPU intervention A special wrap around mode lets the user continuously sample a serial peripheral automatically updating t...

Страница 39: ...er high performance or low power consumption under software control The system clock is a fully static CMOS design so it is possible to completely stop the system clock via a low power stop instruction while still retaining the contents of the registers and on board RAM 3 3 8 Test Module The test module consolidates the microcontroller test logic into a single block to facilitate production testin...

Страница 40: ...TERNAL RAM 1 XXX7FF 2 OPTIONAL FPCP PFB U5 3 110000 120000 5 ALTERNATE MCU INTERNAL MODULES LOCATION 4 1 Consult the MCU device user s manual 2 XXbase address is user programmable Internal modules such as internal RAM can be configured on power up reset by using the initilization table INITTBL covered in Appendix C of the M68MPCBUG Debug Monitor User s Manual M68MPCBUG AD1 3 Floating point coproce...

Страница 41: ...ode is implemented in MCU microcode In background mode registers can be viewed or altered memory can be read or written and test features can be executed Background mode is initiated by one of several sources externally generated breakpoints internal peripherally generated breakpoints software and catastrophic exception conditions Instruction execution is suspended for the duration of background m...

Страница 42: ... on sequential instruction execution by the CPU and coprocessor For optimum performance the coprocessor interface lets floating point instructions execute concurrently with CPU integer instructions Concurrent instruction execution is further extended by the coprocessor which executes multiple floating point instructions simultaneously 3 6 2 Logic Analyzer Connectors To debug hardware and software ...

Страница 43: ...a book or technical summary For a complete description of the SCSI signals consult the appropriate NCR 53C90B User Manual Data Book For a complete description of the P2 P3 signals consult the appropriate MOTOROLA M68681 User Manual Data Book Tables 4 1 through 4 19 list pin assignments for these connectors Table 4 1 SCSI connector P1 not populated Table 4 9 Logic analyzer connector POD1 Table 4 2 ...

Страница 44: ...US bit 3 Bit 3 of the SCSI bi directional data bus lines 9 GND GROUND 10 SDB4 SCSI DATA BUS bit 4 Bit 4 of the SCSI bi directional data bus lines 11 GND GROUND 12 SDB5 SCSI DATA BUS bit 5 Bit 5 of the SCSI bi directional data bus lines 13 NC Not Connected 14 SDB6 SCSI DATA BUS bit 6 Bit 6 of the SCSI bi directional data bus lines 15 GND GROUND 16 SDB7 SCSI DATA BUS bit 7 Bit 7 of the SCSI bi direc...

Страница 45: ...ve low output signal that indicates a reset condition All devices using the bus must release it 41 GND GROUND 42 MSG MESSAGE Active low output signal that indicates the target is sending a message 43 GND GROUND 44 SEL SELECT Active low output signal used by the MPC505 to select a target 45 GND GROUND 46 C D CONTROL DATA Active low output signal that indicates whether control of data is on the data...

Страница 46: ...C serial input signal 3 ATXD TRANSMIT RS 232C serial output signal 4 ADTR DATA TERMINAL READY An output line that indicates an on line in service active status 5 GND GROUND 6 ADSR DATA SET READY An output signal held high that indicates an on line in service active status 7 ARTS REQUEST TO SEND An input signal used to request permission to transfer data 8 ACTS CLEAR TO SEND An output signal that i...

Страница 47: ...C serial input signal 3 BTXD TRANSMIT RS 232C serial output signal 4 BDTR DATA TERMINAL READY An output line that indicates an on line in service active status 5 GND GROUND 6 BDSR DATA SET READY An output signal held high that indicates an on line in service active status 7 BRTS REQUEST TO SEND An input signal used to request permission to transfer data 8 BCTS CLEAR TO SEND An output signal that i...

Страница 48: ...mission to transfer data 5 CCTS CLEAR TO SEND An output signal that indicates a ready to transfer data status 6 ADSR DATA SET READY An output signal held high that indicates an on line in service active status 7 GND GROUND 8 CDCD DATA CARRIER DETECT An output signal used to indicate an acceptable received line carrier signal has been detected 9 19 NC Not Connected 20 ADTR DATA TERMINAL READY An ou...

Страница 49: ...ing reset 3 GND GROUND 4 DSCK DEVELOPMENT SERIAL CLOCK Serial input clock for background debug mode 5 GND GROUND 6 VFLS1 VISIBILITY FLUSH If VFLS0 and VFLS1 are high the MPC505 is in background debug mode 7 RESET RESET Active low input signal that resets the MPC505 MCU 8 DSDI DEVELOPMENT SERIAL DATA IN Serial data input signal for debug mode 9 VCC 5 VDC POWER Input voltage 5 Vdc 2 0 A used by the ...

Страница 50: ...of the three state output address bus B 5 BSWE0 Address signal A6 one signal of the three state output address bus B 6 B 9 CS4 CS1 CHIP SELECT 4 1 Output signals that select peripheral memory devices at programmed addresses B 10 B 29 GND GROUND B 30 CLKOUT SYSTEM CLOCK OUT Output signal that is the MPC505 MCU internal system clock B 31 B 32 GND GROUND C 1 BSWE3 Address signal A9 one signal of the ...

Страница 51: ...VDDSYN Clock synthesizer power A 6 A 8 IRQ6 IRQ4 INTERRUPT REQUEST 6 4 Prioritized active low input lines that requests MCU synchronous interrupts IRQ1 has the highest priority A 9 A 12 CT0 CT3 CYCLE TYPE SIGNALS Four bits that indicate what type of bus cycle the bus master is initiating A 13 GND GROUND A 14 A 16 VF0 VF2 VISIBILITY FETCH Instruction queue status bits that indicate the last fetched...

Страница 52: ...s the EVB A 28 A 29 VFLS1 VFLS0 VISIBILITY FLUSH History buffer flush status bits that indicate how many instructions are flushed from the history buffer during the current clock cycle Also indicates the freeze state A 30 DSDI DEVELOPMENT SERIAL DATA IN Serial data input signal for debug mode A 31 DSCK DEVELOPMENT SERIAL CLOCK Serial input clock for background debug mode A 32 DSDO DEVELOPMENT SERI...

Страница 53: ...BURST Active low indicates a burst cycle C 14 C 17 WP0 WP3 WATCHPOINT 0 3 Output signals for instruction bus I bus watchpoint C 18 C 19 WP4 WP5 WATCHPOINT 4 5 Output signals for load store bus L bus watchpoint C 20 NC Not Connected C 21 AT0 ADDRESS TYPES bit 0 One of two output bits that defines address space as user data user instruction supervisor data or supervisor instruction C 22 ECROUT ENGIN...

Страница 54: ... memory devices at programmed addresses 10 13 BSWE0 BSWE3 Address signal A6 A9 one signal of the three state output address bus 14 19 A10 A15 ADDRESS BUS bits 10 15 6 pins of the three state output address bus 20 GND GROUND Table 4 10 Logic Analyzer Connector POD2 Pin Assignments Pin Mnemonic Signal 1 3 NC Not Connected 4 17 A16 A29 ADDRESS BUS bits 16 29 14 pins of the three state output address ...

Страница 55: ...g mode 6 DSDO DEVELOPMENT SERIAL DATA OUT Serial data output signal for debug mode 7 9 VF0 VF2 VISIBILITY FETCH Instruction queue status bits that indicate the last fetched instruction or the number of instructions flushed from the instruction queue 10 11 VFLS0 VFLS1 VISIBILITY FLUSH History buffer flush status bits that indicate how many instructions are flushed from the history buffer during the...

Страница 56: ...vation 12 BR BUS REQUEST Active low input signal that indicates that an external device requests bus mastership 13 BB BUS BUSY Active low bi directional signal asserted by the current master that indicates that the bus is in use 14 BG BUS GRANT Active low input signal that indicates that an external device has assumed control of the bus 15 16 IRQ0 IRQ1 INTERRUPT REQUEST 0 1 Prioritized active low ...

Страница 57: ...ignals where one byte enable controls one byte lane of the data bus 12 BDIP BURST DATA IN PROGRESS An active low output signal that indicates the data beat in front of the current one is needed by the master 13 R_W READ WRITE Active high output signal that indicates the direction of data transfer on the bus 14 TS TRANSFER START An active low output signal that indicates the start of a bus cycle 15...

Страница 58: ...SUPPORT INFORMATION 4 16 MPC505EVBUM D ...

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