Motorola MCU M68MPB916R3, Руководство пользователя

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MEVB SUPPORT INFORMATION
4-6 M68MPB16R3UM/D
Table 4-6. Logic Analyzer Connector J12 Pin Assignments (continued)
Pin Mnemonic Signal
17 SIZ0 TRANSFER SIZE – Output signal that indicate the
number of bytes still to be transferred during this
cycle.
18 R/W READ/WRITE – Output signal that indicates the
direction of data transfer on the bus.
19 BGACK /
CSE
BUS GRANT ACKNOWLEDGE – Active-low input
signal that indicates an external device has assumed
bus mastership.
EMULATOR CHIP SELECT – Output signal that
selects external emulation devices at internally-
mapped addresses. CSE is used to emulate I/O
ports.
20 GND GROUND
Table 4-7. Logic Analyzer Connector J13 Pin Assignments
Pin Mnemonic Signal
1 +5V +5 VDC POWER – Input voltage (+5Vdc @ 1.0 A)
used by the MEVB logic circuits. (To make this pin a
no connection, remove the jumper from jumper
header W21 on the MPFB.)
2 SPARE No connection
3 DSACK1 DATA AND SIZE ACKNOWLEDGE 1 – Active-low
input signal that allows asynchronous data transfers
and dynamic bus sizing between the MCU and
external devices.
4 AVEC AUTOVECTOR – Active-low input signal that
requests an automatic vector during interrupt
acknowledge.
5 HALT HALT – Active-low input/output signal that suspends
external bus activity, to request a retry when used
with BERR, or for single-step operation.
6 AS ADDRESS STROBE – Active-low output signal that
indicates a valid address is on the address bus.