TRANSCEIVER 400 MHz
MTP700 Portable Radio / Detailed Service Manual
4.1 - 35
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
G
MUX_CTRL=1
RX
Vss
R318
NOTE: RESETS FROM THE BOTTOM CONNECTOR WILL ONLY BE POSSIBLE IF
MUX_CTRL =1 AND THE 8-WIRE INTERFACE IS THUS SET TO JTAG MODE
RX
TX
SCKA
SC2A
GPCR (Bit7)=0
RESET_IN
TCK
4-Wire RS232
STDA
SRDA
TDO
(U302)
DNP
DNP
DNP
TRST
Type of SRAM
ESSI
INT6
INT7
Core Voltage Convertors
X
AND GATE
GPCR (Bit7)=1
EMUL port
QSPI & L1T & BBP
Bottom, GPIO, JTAG, DEBUG, DATA,STO
Clock Output Driver
DSP_DE
CTS
RTS
DSR
DTR
MCU_DE
E3
8-Wire RS232
RTS
RX
SIM CARD
ESSI
TX
RX
256K x 16 SAMSUNG
X
BUSY_OUT
Bus Control
NOT GATE
Data Bus
TX
RI
SCKA
512K x 16 CYPRESS
X
MUX_CTRL=0
SC2A
STDA
SRDA
DSP DATA visibilty
JTAG
CTS
Audio Codec Port
TX
ROW7
ROW6
Gen Port Ctrl Reg (GPCR)
Gen Port Ctrl Reg (GPCR)
X
REDCAP2
BUSY_IN (IC2)
TDI
RTS
8 Mb
64 Mb
GPCR = xxxxxxxx x00xxx00
TMS
WR_
DNP
A21
Address Bus
DSP Address visibilty
DCD
CTS
CYPRESS 512k x16
CS2
R319
256K x 16 CYPRESS
512K x 16 SAMSUNG
DNP
Internal Core
PWM1_1.8V
7
8
SYMBOL
PIN NAME
SB9600
FLASH
4 M x 16
EB1#
Bypass Caps for REDCAP
GPCR = xxxxxxxx x11xxx11
A6
DNP
A18
B3
EN_WE
EN_WP
A5
E8
GND1
F1
GND2
C4
NC1
F5
VCC
E1
VCCQ
A4
VPP
D3
DQ5
DQ6
E3
DQ7
F2
DQ8
D6
DQ9
E6
D7
EN_CE
F8
EN_OE
B4
EN_RP
DQ11
D4
DQ12
E4
DQ13
F3
DQ14
D2
DQ15
E2
DQ2
D5
DQ3
E5
DQ4
F4
B7
A5
C6
A6
A7
A7
A3
A8
C3
A9
DQ0
E7
DQ1
F7
DQ10
F6
D1
A16
B6
A17
B5
A18
A6
A19
B8
A2
C5
A20
C7
A3
A8
A4
D8
A0
C8
A1
B2
A10
A2
A11
C2
A12
A13
A1
B1
A14
C1
A15
28F320C3
U303
14
1
4
150pF
C310
18
RS232_CTS
RS232_RTS
RS232_RX
0.1uF
MUX_CTRL
RS232_TX
RS232_DCD
RS232_RI
C326
GND
3
INA
2
INB
1
OUTY
4
VCC
5
0
C328
U304
TC7S08FU
5109522E22
0.1uF
C301
0.1uF
4
2
C319
0.1uF
.01uF
C300
3
0.1uF
C324
0.1uF
C315
11
VCC1
D6
VCC2
E1
14
IO7
G6
IO8
B1
IO9
C1
NC1
A6
NC2
E3
NC3
G2
NC4
H1
NC5
H6
IO13
F2
IO14
F1
IO15
G1
IO2
C6
IO3
D5
IO4
E5
IO5
F5
IO6
F6
EN_WE
G5
GND1
D1
GND2
E6
IO0
B6
IO1
C5
IO10
C2
IO11
D2
IO12
E2
A6
C4
A7
D4
A8
H2
A9
H3
EN_BHE
B2
EN_BLE
A1
EN_CE
B5
EN_OE
A2
A14
F3
A15
F4
A16
E4
A17
D3
A2
A5
A3
B3
A4
B4
A5
C3
U302
CY62147V
A0
A3
A1
A4
A10
H4
A11
H5
A12
G3
A13
G4
R315
F9
J11
QVCCH2
QVCCH3
M8
QVCCH4
K3
6.8K
QGND2
L1
QGND3
L7
QGND4
L16
QVCC1
F8
QVCC2
L4
QVCC3
L13
QVCC4
M7
QVCCH1
NC3
G8
NC4
G9
NC5
G10
NC6
H7
NC7
H8
NC8
H9
NC9
H10
QGND1
F10
NC13
J10
K7
NC14
K8
NC15
K9
NC16
K10
NC17
L6
NC18
L11
NC19
NC2
G7
B1
LVDD
MGND
L9
MVDD
L8
NC0
F6
NC1
F11
NC10
J7
NC11
J8
NC12
J9
M12
T16
GVDD3
A7
HGND1
HGND2
A11
HVDD1
B11
C8
HVDD2
KGND
E14
KVDD
E16
C1
LGND
EVDD
B15
FGND
L3
FVDD
M4
GGND1
H15
GGND2
K16
T15
GGND3
GVDD1
H16
GVDD2
G1
AVDD2
J5
BGND
P11
BVDD
R11
CGND
N4
CVDD
N1
DGND
T5
DVDD
R5
EGND
C16
PWR_GND_NC
U301-2
AGND1
G2
AGND2
K5
AVDD1
10
1.0uF
C309
13
0.1uF
C318
15
16
5
6
8
10
11
12
13
14
9
10
3
9
C308
0.1uF
150pF
SHIELD
SH301
1
C307
14
15
3
4
3
8
5
TCXO_WARP
7
10uF
C312
7
12
5
R318
0
0.1uF
6
1
19
C314
0
21
R309
6
V3_2.775V_DIG
C302
0.1uF
10uF
13
C329
9
R316
12
13
4
8
20
5
6
9
2
15
16
17
1
2
19
.01uF
4
C320
C317
R319
.01uF
1.0uF
0
C311
C322
.01uF
C327
.01uF
SHIELD
SH300
1
C316
0.1uF
2
0
11
3
6
3
4
RS232_DSR
C325
.01uF
7
1
2
C303
.01uF
1
RESET_OUT
1
5
R310
0
0.1uF
12
RS232_DTR
15
C323
0.1uF
C313
17
18
11
GND
3
IN_A
2
NC
1
OUT_Y_
4
VCC
5
VCC
5
VREF1_2.775V
5102463J77
MC74HC1G04
U305
U307
TC7S08FU
GND
3
INA
2
INB
1
OUTY
4
C321
V3_2.775V_DIG
V3_2.775V_DIG
10
0.1uF
RS232_DSR
HST_DATA(0:15)
HST_Addr(0:21)
MEM_CNTL(6:1)
DSP_3
RS232_CTS
RS232_RTS
RS232_RX
RS232_TX
MUX_CTRL
RS232_RI
RS232_DCD
RS232_DTR
DSP_1
DSP, Controller & Memory Schematic Diagram (Memory)
Содержание IMPRES Tetra MTP700
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