TRANSCEIVER 400 MHz
MTP700 Portable Radio / Detailed Service Manual
4.1 - 19
RedCap2 (Microprocessor & DSP)
Figure 4.1-10 RedCap2 - Block Diagram
Figure 4.1-10 is a block diagram of the RedCap2 and its interfaces.
The RedCap2 RISC processor controls the operation of the transmitter, receiver, synthe-
sizer and audio (GCAP3) integrated circuits. It uses the Flash memory and SRAM, both
located externally.
RedCap2 employs SPI protocol (Serial Peripheral Interface) to communicate with the RF
ICs, display, keypad and other internal peripherals. The processor can be operated
through the RS232 interface by a personal computer to program the Flash memory with
firmware and codeplug.
Within the RedCap2 is the Digital Signal Processor (DSP) which performs modulation
and de-modulation functions for the radio. It also performs ACELP speech coding and
Forward Error Correction.
Encryption
Accelerator
DSP Peripheral
DMA
PROM 2Kx24
PRAM 40Kx24
YROM 0Kx16
YRAM 15Kx16
DSP
Core
Viterbi
Accelerator
MCU/DSP
Interface
MDI
XROM 0Kx16
XRAM 12Kx16
Shared X/VIAC
RAM 2Kx16
Shared X/MCU
RAM 2Kx16
Clocks/PLL
MCU Debug
Layer 1
Timer
JTAG/OnCE
UARTB
M
U
X
UARTA
Audio
CODEC
Serial Port
SAP
BRM
External
Inteface
Module
QSPIB
QSPIA
SIM
Reset
Keypad
Interface
GPIO
MCU
Core
ROM 4Kx32
RAM 512x32
PIG
Peripheral I/F
Gasket
GPReg
MCU Timers/
PWM/PIT/
Watchdog
Baseband
CODEC
Serial Port
BBP
Counter
DSP Timer
MCU Int.
Ctl
DSP_IRQ
STDB
SRDB
SFSB(2)
SCKB(2)
STDA
SRDA
SFSA(2)
SCKA(2)
ADRS(22)
DATA(16)
R/W
OE
EB0,EB1
CS(6)
MOD
INT(6)
INT6/DSRA/
STDA/TRST
INT7/DTRA/SCLK/
SRDA/TMS
MOSIB
MISOB
QSCKB
SPICSB(5)
MOSIA
MISOA
QSCKA
SPICSA(5)
RST_OUT
RST_IN
COLUMN(5)
ROW(5)
COLUMN5/GPIO
ROW5/IC2B/GPIO
COLUMN6/OC1
COLUMN7/PWM
ROW6/DCDA/SC2A/DSP_DE
ROW7/RIA/ISCKA//TCK
XYA(16)
XYRW,XYSEL,XYSTB
XYD(16)/TXA/RXA/GI
CKIH,CKIL
CKOH,CKO
DEBUG(6)
TOUT(16)
DSP_DE
JTAG(5)
MCU_DE
TEST
RTSB
CTSB
TXB
RXB
MUX_CTL
RTSA/IC2A/
RESET_IN
CTSA/MCU_DE
TXA/TDO
RXA/IC1/TDI
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