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DSP56F801EVM Hardware User’s Manual
2.5 Debug Support
The DSP56F801EVM provides an on-board Parallel JTAG Host Target Interface and a
JTAG interface connector for external Target Interface support. Two interface connectors
are provided to support each of these debugging approaches. These two connectors are
designated the JTAG connector and the Host Parallel Interface Connector.
2.5.1 JTAG Connector
The JTAG connector on the DSP56F801EVM allows the connection of an external Host
Target Interface for downloading programs and working with the DSP56F801’s registers.
This connector is used to communicate with an external Host Target Interface which
passes information and data back and forth with a host processor running a debugger
program.
shows the pin-out for this connector.
When this connector is used with an external Host Target Interface, the parallel JTAG
interface should be disabled by placing a jumper in jumper block JG5. Reference
for this jumper’s selection options.
Table 2-2. JTAG Connector Description
J8
Pin #
Signal
Pin #
Signal
1
TDI
2
GND
3
TDO
4
GND
5
TCK
6
GND
7
NC
8
KEY
9
RESET
10
TMS
11
+3.3V
12
NC
13
NC
14
TRST
Table 2-3. Parallel JTAG Interface Disable Jumper Selection
JG5
Comment
No jumpers
On-board Parallel JTAG Interface Enabled
1–2
Disable on-board Parallel JTAG Interface
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