Motorola APX 7500, Подробное руководство по обслуживанию

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September 9, 2011 68009482001
2-6 Theory of Operation: System Communications Overview
• SPI_MISO: SPI input serial data
• SPI_MOSI: SPI output serial data
• SPI_CLK: SPI Clock
2.3.9 Main SSI Bus
The main SSI bus is used by OMAP to transfer data to the FPGA. This SSI Bus uses a 1.536 MHz
clock, 8 kHz Frame sync, 16 bit word size, and 12 slots. The FPGA is also the clock master for this
SSI bus, generating clock and frame sync.
Main SSI Signals:
• SCLK: Main SSI Clock running at 1.536 MHz
• FS: Frame sync running at 8 KHz
• STDA: SSI Transmit data
• SRDA: SSI Receive data
2.3.10 Nautilus FPGA Control signals
FGPA control signals are mainly used to know FPGA status, programming status and reset.
FPGA Control signals:
• NAUT_RESET*
• NAUT_INT
• NAUT_STATUS
• NAUT_CONFIG
• NAUT_CONFIG_DONE
2.3.11 USB Connectivity
The Consolette Mainboard has two USB ports for communication. A USB full speed device port
(USB 1.1 compliant) and a USB Host port (version 1.1 compliant) that supports low and full speed.
2.3.12 USB Device port
The USB device port uses the internal OMAP transceiver which is connected to Pin Group 0. The
OMAP USB transceiver transmits and receives serial data at full speed 12 Mbit/sec.
The enumeration process starts when a USB device connection is made to a USB host such as a
computer. The USB device port detects VBUS and then pulls up D+ with a 1.5kOhm resistor inside
FL1500. The host detects the D+ pull up and starts the enumeration process; activity should be seen
on differential signals D+ and D-. See
Figure 2-1 for USB full speed screen capture. Filter ST202 is
used to protect the USB device port from ESD and RFI. The USB device port uses a standard USB
type B connector.