Example:
Apply the Schaevitz 4000HR LVDT. It has a stroke of ±100mm
and a sensitivity of 8.8mV/ V/mm.
At full stroke of 100mm this equates to a sensitivity of
0.88V/ V.
The manufacturer’s recommended excitation is 3.0V RMS at
2.5kHz.
Adjust the osc. level pot so the output is 3.0V RMS
(
Vac
= 1.5V RMS). The full scale secondary voltage will be
2
3 x 0.88 = 2.64V RMS, just below the secondary maximum of
0.9 x 3.0 = 2.70 VRMS.
If the oscillator level is set to 8.0V RMS, the full stroke
secondary level would be 0.88 x 8 = 7.04V RMS. This is less
than the secondary maximum of 7.2 VRMS and the absolute
maximum of 8.0 VRMS, so the oscillator level can be safely set
up to the maximum of 8.0V RMS.
5.3 Secondary phase difference
The G123-817-006 circuit uses the primary signal to
synchronously detect the secondary signal. Phase differences
between these signals can cause minor errors and so there is
the facility on the circuit card to null phase differences.
Withdraw the circuit card from its case and connect a dual
channel oscilloscope to primary TP
Vac
and secondary
TP2
.
2
Move the LVDT core until
TP2
has a signal that is noise free
and easy to read. The signal will be too small near null.
Determine if the secondary is leading or lagging the primary
signal. Select lead or lag. Do not select lag and lead together.
Now monitor the secondary
TP2
and the phase adjusted
secondary demod signal on
TP3
. Adjust the phase pot
R6
until
these two signals are in phase. Select the appropriate lag or
lead capacitors to enable the best phase match. Note that R6
is a 25 turn pot.
Switches
S2-7
and
S2-8
select the two lag capacitors, which
are switched in parallel. Switches
S2-1
to
S2-3
and
S2-4
to
S2-6
select the lead capacitors, which are switched in series.
To maintain a balanced circuit the switches should be paired in
the same positions. The pairs are
1
and
2
,
3
and
4
,
5
and
6
.
The minimum phase angle varies with frequency and is
typically 3° to 8°. If the phase error is less than 3° to 8°, it
cannot be reduced and so no phase adjustment may give the
minimum phase error.
5.4 Output zero
Move the LVDT core to its required centre position and adjust
the front panel
zero
pot. until the level on the
output
test
point is 0V. Set to 12mA if using the 4-20mA signal output.
5.5 Output span
Move the LVDT core to its required full stroke position and
adjust the front panel
span
pot
until the level on the
output
test point is 10V. If the polarity is opposite to that required,
interchange the secondary wires on terminals 9 and 12.
Re-check the
zero
setting. Increasing the
oscillator level
will
not increase the output. If 10V output cannot be achieved,
consult Moog. Double check the waveform distortion to ensure
the oscillator is not over loaded. Set to 20mA if using the
4-20mA signal output.
6 Withdrawing the circuit card
from its case
In order to set the oscillator frequency, select phase lag or lead,
or to adjust the phase angle, the circuit card needs to be
withdrawn from its case.
To do this, push one tab in with a pen or screwdriver while
gently pulling on the top cover on that side. The cover will
release approximately one mm. Repeat on the other side and
withdraw the cover and circuit card until the required
adjustment points are exposed. The rigidity of the connecting
wires will hold the circuit card in position while adjustments
are made.
LVDT
13
14
9
12
10
11
S2-8
2200
pF
pF
680
S2-7
1K5
R6
100K
10K
S2-1
S2-2
S2-3
S2-4
S2-5
S2-6
10K
10K
6.8nF
6.8nF
15nF
15nF
47nF
47nF
TP2
DEMODULATOR
SECONDARY
AMPLIFIER
PHASE ADJUSTMENT CIRCUIT
OSCILLATOR
+1
+1
TP3
SECONDARY
SIGNAL
TEST POINT
ADJUST FOR MINIMUM
PHASE DIFFERENCE
SECONDARY
DEMOD
TEST POINT
LEAD
LAG
VAC
2
Front Panel
2
(P.C.B.)
(P.C.B.)
Phase adjustment circuit
Page 3 of 4: C70880 Rev
E – 11.15
