DB[0~9]
2~11
36
VID1
DAC
Control Logic
and
DAC Latches
34
VID2
DAC
32
VID3
DAC
30
VID4
DAC
28
VID5
DAC
26
VID6
DAC
AMP
AMP
AMP
AMP
AMP
AMP
CLK
48
STSQ
46
XFR
47
INV
15
E/O
13
R/L
14
BIAS
STBY
20
BYP
21
SCALING
CONTROL
VREF
40
VMID
39
38
V2
43
V1
INVERT LEVEL SHIFT
41
DY
LEVEL SHIFT
INVERT LEVEL SHIFT
LEVEL SHIFT
INVERT LEVEL SHIFT
DELAY CIRCUIT
REFERENCE
CLOCK
PHASE COMPARISON
CIRCUIT
DELAY CIRCUIT
DELAY CIRCUIT
DELAY CIRCUIT
DELAY CIRCUIT
DELAY CIRCUIT
DECODER
INVERT LEVEL SHIFT
LEVEL SHIFT
INVERT LEVEL SHIFT
INVERT LEVEL SHIFT
INVERT LEVEL SHIFT
INVERT LEVEL SHIFT
INVERT LEVEL SHIFT
39
40
26
35
45
38
32
33
34
28
29
30
31
22
46
14
5
4
3
47
45
6
11
9
16
17
8
10
CLY
DIRY
NRG
ENBY2
MONITOR
CLX
ENBX1
ENBX2
ENBX3
ENBX4
DYIN
CLYIN
DIRYIN
LEVEL SHIFT
27
15
DIRX
DIRXIN
NRGIN
MODE
44
CMODE
CLK
RST
7
DXIN
CLXIN
ENBX1IN
ENBX2IN
ENBX3IN
ENBX4IN
NRSW1
NRSW2
2,12
1,13
23,37,43
24,25,36,42
SW
SW
SW
SW
19
18
VCC GND
VDD
DGND
NRSA
NRSB
21
NRSD
20
NRSC
TEST
48
(VDD System)
(VCC System)
NRS
CLX
DX
CLY
IC8A1,IC8M1 L3E06090D0A
IC8A2,IC8M2 L3E01040F0A
PCB-MAIN(5/8)
PCB-MAIN(6/8)
B-4
1
2
3
4
6
5
7
8
9
18
17
16
15
14
13
12
11
10
H SYNC DET.
SYNC SEPA.
V SYNC SEPA.
V SYNC DET.
CLAMP PULSE GEN.
HOR. SYNC
CONTROL
HSCTL
C / HSYNC IN
VIDEO IN
VSEPA
VSYNC IN
CVPOL
CVEXI
CPSEL
GND
POLH
EXIH
POLV
EXIV
Vcc
HDRV
CLAMP
VDRV
CPWID
IC7A2 HD74LV14T
400k
7
10
T2 IN
T2 OUT
12
R1 OUT
13
R1 IN
5k
9
R2 OUT
8
R2 IN
5k
5
C2-
16
4
C2+
3
C1-
Vcc
1
C1+
V-
6
V+
2
R1
R2
GND
15
T2
400k
14
11
T1 IN
T1 OUT
T1
TTL/CMOS
INPUT
TTL/CMOS
OUTPUT
RS-232
OUTPUT
RS-232
INPUT
+5V to +10V
Voltage Doubler
+10V to -10V
Voltage Inverter
The negative terminal of the V+ storage capacitor can be tied
to either Vcc or GND. Connecting the capacitor to Vcc (+5V)
is recommended.
IC7H2 SP232ECN
PCB-MAIN(7/8)