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WVGA
I2C
Addrres
0x3*
1_Chip_DDR_Mode_1
W
A
IT
_t
rigger
0:
all_t
he_t
ime
W
A
IT
_logic
1:
C
hip_s
elec
te
d
1:
Priorit
y
0:
N
o_c
hange
Endian_change (Graphic
s)
change(2By
te)
1:
H
igh=R
eady
0:
Low
=R
eady
324MHz
NC
VSS
NC
CNT
CNT
VIN
VSS
VOUT
VSS
VSS
I2C
VIN
512Mb
/
x16
DDR2-SDRAM
VOUT
To Cammue DDR2
To HDMI,LVDS,Cammue
IC6C5
CPUP_A5
CPUP_A1
DDR2_CS*
DDR2_ZQ
DDR2_VREF
NJ3_EX_D<15..0>
R6
K
9
OPEN
4.
7k
R
6L4
NJ3_EXCS0_4*
NJ3_WE1*
CAMMUE_WAIT*
DOTCLKOUT
CAMMUE_SCL
CAMMUE_RESET*
4.
7k
6B2<>
4.
7k
R
6L3
GND1
R6M2
CAMMUE_INT
19D1<
14
+3.3V
12
DDR2_CKE
DDR2_ODT
DDR2_DQ15
DDR2_A4
DDR2_A9
NX3225GA
27.000MHZ
0
DOTCLKOUT
R6N0
GND1
NC
4
CPUP_CLK
33
W1
Low
ESL
C
6L2
0.
1u
D6J6
25V
(X6S)
0.1u
C6K2
(X7R)
6
0
DDR2_DQ0
CPUP_D15
CPUP_D14
1k
D3
DDR2_DQ1
OPEN
T9
NA_IO
NA_IO
DDR2_UDQS
DDR2_LDQS
DDR2_LDQS*
DDR2_LDM
Low
ESL
S-1172B18-E6T1G
11
C6J9
25V
GND1
10u 6.
3V
+1.8V
1k
1.5k
R6M5
TP6G4
T2
R6M1
D18
A8
I2C_SDA
I2C_SCL
CPUS_SDA
CPUS_SCL
CPUP_RD*
CPUP_D0
CPUP_D1
V5
T6
CPUP_D13
(X6
S)
6.
3V
R
6L7
RST*
NA_IO
NA_IO
NA_IO
NA_IO
NA_IO
NA_IN
NA_IN
A9
R4
Y11
D2
C1
E4
DDR2_UDM
F18
DDR2_UDM
GND1
+1.8VDDR
4.
7k
H19
+3.3V
19A1<
4
3
GND1
1
3
2
R6
J8
GND1
OUT
22F8>
GND
CD
VDD
DDR2_DQ<15..0>
C
6L4
6
10
4.
7k
4.
7k
+3.3V
V4
CPUP_A3
DDR2_DQ3
G19
0.01u
GND1
C
6L8
C
6L9
0.
1u
10V
C6
M2
10u
4
(X7R)
25V
0.01u
C6L0
6.3V
(X6S)
0.1u
C6K1
Low ESL
7
R19
K17
K19
R6
J9
D6J5
RA6J7
DDR2_A5
T19
R18
NJ3_EX_A<7..1>
8
6
GND1
+2.5V
GND1
GND1
2
1
6.3V
(X6S)
0.1u
C6K3
(X6S)
Low ESL
11
10
15
+3.3V
2
R6N9
R6N6
R6N5
R6N4
R6N2
R6
M8
R6
M3
R6M0
R6L1
R6
K
6
R6
K
0
RA6J8
RA6K2
IC6J8
GND1
Low
ESL
(X6
S)
9E2<
+1.8VDDR
1k
-D
6.
3V
-D
GND1
1k
(X7R)
6.3V
Low ESL
(X6
S)
6.
3V
5
9
1
12
8
14
13
3
GND1
Low
ESL
25V
6.3V
6
7
4
0
2
+1.8VDDR
GND1
0.1u
Low
ESL
0.1u
Low
ESL
(X6S)
(X6S)
6.3V
6.3V
Low
ESL
Low ESL
0.01u
(X7R)
Low
ESL
25V
+1.8VDDR
0.
1u
10V
GND1
6.
3V
GND1
1
2
GND1
3
S-1172B18-E6T1G
A
K
6
5
6.
3V
GND1
GND1
13
11
12
9
10
15
12
13
11
10
9
8
7
6
5
8
7
5
3
1
2
0
3
4
2
1
0
1
4
3
2
5
9
12
13
1
0
-D
1k
-D
1k
+1.8V
GND1
S1G
3
6
5
GND1
0.
1u
6.
3V
(X6
S)
GND1
5
6
8
7
5
4
1
2
3
4
1
2
3
4
5
6
7
8
7
5
5
7
6
8
7
3
4
2
1
4
2
3
2
1
33
6
3
5
8
6
5
7
1
4
3
33
33
1
2
15
11
9
10
7
8
6
4
5
2
1
5G2<
22D10<>
1k
1k
1k
0
GND1
8
5
7
6
TP6G2
0
0
4
1
1k
2
LDQS
UDM
4.
7k
2
C6
J6
C6J8
C6K4
C6K5
C6
K
7
C6K8
C6K9
+1.8VDDR
UDQS
1k
R6N3
2
3
1
TP6G0
TP6G1
GND1
GND1
GND1
S1G
GND1
4
GND1
GND1
+2.5V
1k
4
GND1
14
R6
K
8
DDR2_BA<2..0>
DDR2_A<13..0>
DDR2_CK
DDR2_CK*
DDR2_UDQS
DDR2_ODT
DDR2_CKE
DDR2_CS*
DDR2_RAS*
DDR2_CAS*
DDR2_WE*
GND1
4.
7k
22C4>
DDR2_UDQS*
DDR2_A8
DDR2_A7
DDR2_A6
T20
CPUP_A7
CPUP_A6
W4
DTST_TCK
DTST_TDO
XOUT
DDR2_VREF2
T18
DDR2_DQ8
DDR2_DQ7
DDR2_DQ5
DDR2_DQ2
DTST_TDI
CPUP_A4
D10
V17
Y15
Y3
CPUP_D2
CPUP_D3
CPUP_D4
CPUP_D6
V2
P20
V20
U18
DDR2_DQ14
C2
B1
C10
C9
B10
W14
U10
U9
T4
Y2
U1
T1
R5
W3
Y4
U7
U5
U6
W5
V6
Y5
V7
W6
Y7
V1
U3
U2
BSMODE
DDR2_RAS*
R16
L16
M18
N17
M17
L19
M20
DDR2_CK*
DDR2_DQ10
DDR2_CK
J17
N20
N19
H17
G17
H18
G18
F19
H20
F20
T17
R20
R17
P19
DDR2_A10
U19
W20
P18
M19
TEST1
DDR2_DQ13
DDR2_DQ11
L18
K20
R6
K
5
1
NC
5B3<>
13
R6
J7
GND1
Y6
DDR2_LDQS*
-D
R6L8
8
CPUP_D11
R
6L9
33
L20
120
LDQS*
Low
ESL
C6
J5
DDR2_UDQS*
DDR2_LDQS
C
6L3
10V
0.
1u
4.
7k
4.7k
T3
DDR2_WE*
DDR2_CAS*
4.
7k
R6N1
1k
DLL_CLKIN
E17
F17
DDR2_DQ9
OPEN
OPEN
OPEN
OPEN
DTST_TRST
DTST_TMS
D9
R
6L6
4.
7k
4.
7k
OPEN
DDR2_BA2
U8
150
-D
K
25V
R6M9
R6N8
R6N7
TP6G3
GND1
1k
R6M7
GND1
+3.3V
CPUP_D5
8
0
22C8>
22G9<
R6M6
X6J5
GND1
(CH)
10p
C
6L6
(CH)
12p
C
6L5
C
6L7
10u 6.
3V
IC6J7
A
DDR2_A3
150
3
0
+1.8VDDR
DQ2
0.
1u
+1.8VDDR
DQ14
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VDD
VDD
VDD
VDD
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSSDL
VDDL
VREF
DDR2_LDM
DDR2_BA1
DDR2_BA0
V19
U20
D9
R7
R3
R8
H2
H8
L1
G2
N8
G8
H7
H3
H1
F1
F9
C8
B1
B9
N3
N7
P2
R2
L2
L3
E1
K7
L8
K2
K8
F3
B3
E8
F7
A8
B7
K9
J7
J1
J2
P9
N1
J3
E3
A3
R1
M9
J9
A1
G9
G7
G3
G1
E9
C9
C7
C3
C1
A9
F8
F2
E7
B8
E2
A2
J8
K3
L7
A7
D8
P8
D2
B2
D1
D3
D7
C2
R6
K
7
0.
1u
Low
ESL
H9
DQ6
P3
BA1
M2
0
1
A3
P7
A6
N2
M7
M3
M8
UDQS*
LDQS*
CS*
VSSQ
WE*
CAS*
RAS*
CKE
CK*
CK
LDM
UDM
LDQS
UDQS
ODT
A0
A1
A2
A3
A4
A5
A7
A8
A9
A10
A11
A12
NC
NC
NC
H5PS5162GFR-Y5J
DDR2_DQ12
G20
J20
K18
J19
L17
DDR2_DQ4
DDR2_DQ6
CPUP_D10
CPUP_D8
CPUP_D7
CPUP_D9
CPUP_D12
4.
7k
4.
7k
4.
7k
OPEN
R
6L0
4.
7k
4
CPUP_IRQ*
OPEN
CAMMUE_SDA
1k
R6
M4
R6P0
R6P1
0
9G2<
19C3<>
19C3<>
4.
7k
NJ3_WE0*
NJ3_RD*
22C4>
22F8>
22F8>
22G9<
3
GND1
GND1
(CH)
22p
C6M3
R
6L2
R
6L5
DDR2_A0
DDR2_A1
DDR2_A2
CPUP_A2
DDR2_A13
DDR2_A12
DDR2_A11
W7
6
8
7
150
R8A64449DBG
IC-PST8428UR
IC6J6
+-30PPM
0.01u
25V
R
6K4
OPEN
GND1
4
68
R6P2
B9
CLKM
CPUP_WAIT
CPUP_WE1*
CPUP_WE0*
CPUP_CS0*
RA6J9
4.
7k
R6K
1
4.
7k
22C5>
5A3<
R6
K
3
GND1
RA6K0
OPEN
5
6
7
RA
6K
1
10u
6.3V
C6K6
5C2<
5C1<
6B4<
6B4<
10D3<
10D3<
VSSQ
VDDQ
(X7R)
C6
M0
10u
C6M
1
(X7R)
0.01u
C6L1
Low
ESL
6.3V
Low
ESL
VDDQ
VSSQ
IC6J5
BA0
Low
ESL
C6K0
0.01u
(X6S)
0.1u
0.01u
0.1u
C6J7
VDD
BA1
2
UDQS*
4.
7k
R6
J5
OPEN
R6
K
2
4.
7k
6B2<
4.
7k
R6
J6
1
2
RA6J6
3
RA6J5
4.
7k
+3.3V
(2/3)
A
A
106
Copyright (C) Mitsubishi Electric Corporation. Your company internal use only.
SCHEMATIC DIAGRAM ANALOG CAMMUE(2/3) CPU I/F MODEL : NR-242UM-13LND0,13-WS