Mitsubishi Electric Apricot LS Pro, Техническое описание оборудования

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System Board
Contents
Chapter 1
Chapter 2
Chapter 3
Chapter 5
Chapter 6
Chapter 3
3/8 LS PRO HARDWARE TECHNICAL REFERENCE
Non-Maskable A non-maskable interrupt (NMI) is generated in the event of a parity or I/O error.
Interrupts Reading Port B indicates the source of the NMI. NMI may be disabled by writing to
I/O address 0070h.
On power up, and after a reset the NMI bit of port 0070h is set to 1 (NMI
disabled). Before NMI is enabled after a power up the I/O channel check state
is initialized by POST.
Note
I/O port 0070h is also used to access the Real Time Clock CMOS RAM, as a result port 0071h
must be read immediately after port 0070h has been written to enabling or disabling NMI.
If this is not done the successful operation of the Real Time Clock and its CMOS RAM cannot
be guaranteed.
Direct Memory Access
Direct Memory Access (DMA) allows data to be transferred to or from system
memory without interrupting the system processor. The DMA controller is
functionally equivalent to two 8237A DMA controllers.
The DMA controller may be programmed by the system microprocessor. The
DMA registers are programmed or read by the system processor addressing
the DMA controller in the ranges shown below.
• hex 0000 to 001F
• hex 0081 to 008F
• hex 00C0 to 00DF
Details on the effect and usage of these addresses is given in section 5.
The two 8237A compatible controllers are cascaded with the DREQ and
DACK signals of channel 0 on one controller connected to the HRQ and HLDA
signals of the other controller. This arrangement results in four 8-bit DMA
channels (DMA1) and three 16-bit channels (DMA2).
The table below shows which DMA channels are allocated which functions.
DMA channels 0 and 1 support memory-to-memory transfers.
DMA channel Function
1 Audio
2 Floppy drive interface
3 Audio
Address In order to access the full 16Mbyte address space of the processor the DMA controller
generation must generate a 24-bit address. The bits 0-7 are taken directly from the 8237A address
outputs, bits 8-15 are latched from the 8237A data outputs while bits 16-24 are from
the appropriate DMA page register.