18
8575
8575
A N/B Maintenance
A N/B Maintenance
Two separate buses, Host-t-GUI in the width of 64 bit, and GUI-t-Memory Controller
in the width of 128
bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or
DDR266 memory subsystem, the 128 bit GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture
transfer rate, respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-
Command Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access
requests from the GUI or AGP controller, Host Controller, and I/O bus masters based on a default optimized
priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering
privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery,
or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to
the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism
is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards
these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by
scheduling the command requests in the background when the data requests streamlines in the foreground.
