114
8575
8575
A N/B Maintenance
A N/B Maintenance
5.6 uPD72872 IEEE1394 Controller
PCI/Cardbus Interface Signals: (52 pins)
Name I/O
PIN
NO. IOL Volts(V)
Function
Block*
PAR
I/O 44 PCI/Cardbus
5/3.3
Parity
is even parity across
AD0-AD31 and
CBE0-CBE3.
It is an input when
AD0-AD31 is an input; it is
an output when AD0-AD31
is an output.
Link
AD0-AD31
I/O 9, 10, 12, 13,
15-18, 23, 24,
26-29, 32, 33,
47-50, 52, 53,
55, 56, 58,59,
62, 63, 65-68
PCI/Cardbus
5/3.3
PCI Multiplexed Address
and Data
Link
CBE0-CBE3
I 21, 34, 45, 57
-
5/3.3
Command/Byte Enables
are multiplexed Bus
Commands & Byte enables.
Link
FRAME
I/O 35 PCI/Cardbus
5/3.3
Frame
is asserted by the
initiator to indicate the
cycle beginning and is kept
asserted during the burst
cycle. If Cardbus mode
(CARD_ON = 1), this pin
should be pulled up to V
DD
.
Link
TRDY
I/O 37 PCI/Cardbus
5/3.3
Target
Ready
indicates that
the current data phase of the
transaction is ready to be
completed.
Link
IRDY
I/O 36 PCI/Cardbus
5/3.3
Initiator
Ready
indicates
that the current bus master is
ready to complete the
current data phase. During a
write, its assertion indicates
that the initiator is driving
valid data onto the data bus.
During a read, its assertion
indicates that the initiator is
ready to accept data from the
currently-addressed target.
Link
Name I/O
PIN
NO.
IOL Volts(V)
Function
Block*
REQ
O
8 PCI/Cardbus
5/3.3
Bus_master Request
indicates to the bus arbiter
that this device wants to
become a bus master.
Link
GNT
I 7
- 5/3.3
Bus_master Grant
indicates to this device that
access to the bus has been
granted.
Link
IDSEL
I
22 -
5/3.3
Initialization Device Select
is used as chip select for
configuration read/write
transaction during the phase
of device initialization. If
Cardbus mode (CARD_ON
= 1), this pin should be
pulled up to V
DD
.
Link
DEVSEL
I/O
39 PCI/Cardbus
5/3.3
Device Select
when actively
driven, indicates that the
driving device has decoded
its address as the target of
the current access.
Link
STOP
I/O
40 PCI/Cardbus
5/3.3
PCI Stop
when actively
driven, indicates that the
target is requesting the
current bus master to stop
the transaction.
Link
PME
O
3 PCI/Cardbus
5/3.3
PME Output
for power
management enable.
Link
CLKRUN
I/O
2 PCI/Cardbus
5/3.3
PCICLK Running
as input,
to determine the status of
PCLK; as output, to request
starting or speeding up
clock.
Link
INTA
O
4 PCI/Cardbus
5/3.3
Interrupt
the PCI interrupt
request A.
Link
