miniDSP NANOSHARC, Руководство пользователя

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miniDSP Ltd, Hong Kong / www.minidsp.com / Features and specifications subject to change without prior notice
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2.5 I2S
EXPANSION HEADER PINOUTS
Headers J2 and J5 are provided for connection of I/O circuitry via I2S. The pinouts are shown in Table 2 and
Table 3. Note that I2C_SCL and I2C_SDA are intended for miniDSP use only – they are not documented or
supported for other use.
Table 2. J2 expansion header pinout
Pin Function Pin Function
1 I2S_LRCLK 2 I2S_BCLK
3 GND 4 MCLK
5 I2S_OUT0 6 I2S_OUT1
7 I2C_SCL 8 I2C_SDA
9 GND 10 GND
11 +12V 12 +12V
Table 3. J5 expansion header pinout
Pin Function Pin Function
1 I2S_LRCLK 2 I2S_BCLK
3 GND 4 MCLK
5 I2S_OUT0 6 I2S_OUT1
7 I2S_OUT2 6 I2S_OUT3
9 GND 10 GND
11 I2S_IN0 12 I2S_IN1
*
13 I2S_IN2
*
14 I2S_IN3
*
* Not accessed by current plugins
2.6 I2S
OVERVIEW
I2S, or Inter IC Sound, is an electrical serial bus used to interface digital audio devices at the chip and circuit
board level. An I2S interface consists of up to three clocks, and a data line for each pair of channels. There are
three types of clock:
MCLK The master clock that the nanoSHARC uses internally. This clock is always provided as an output
by the nanoSHARC, and connected circuitry can choose whether or not to use it.
LRCLK The frame synchronization clock, also known as the word clock. This clock is equal to the
sampling frequency (Fs) of the audio signal.
BCLK The bit clock (also known as shift clock or system clock). This is always equal to 64 x Fs.