System Core 5
miriac EK-5744 User Manual
V 1.2
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© MicroSys Electronics GmbH 2017
5 System Core
5.1 Processor NXP MPC5744
The MPC5744 Qorivva microcontroller is based on an e200 Power Architecture®.
It uses a delayed lock step concept to target the ISO 26262 ASIL-D integrity level.
5.1.1 Processor IO Connections
Pad Signal CPU-I/O Type
Active Description
a3
DOUT0
Output
Data
high
non-inverted output pin state
a5
LDINB#
Output
Stimulus low
global for all digital inputs
a11
DIN0
Input
Data
low
inverted input pin state
a14
HAIN7#
Output
Stimulus low
unique for this analog input
b4
LDINA#
Output
Stimulus low
global for all digital inputs
b12 LAIN#
Output
Stimulus low
global for all analog inputs
b13 DIN2
Input
Data
low
inverted input pin state
b14 PWENA# Output
Enable
low
first stage switch-I enable A
b15 DPWSTD Input
Status
low
first stage switch-II redundant status
Figure 5-1:Processor Block diagram
