VSC8502 Reference Board
VPPD-03822 VSC8502 User Guide Revision 1.0
8
5
Useful Test Features
5.1
Ethernet Packet Generator
ExtMII 29E is the Ethernet Packet Generator register. The EPG sends traffic in multiple of 10,000 frames
regardless of when you stop transmit activity. Refer to the datasheet for configuration options.
A Good CRC packet counter is in ExtMII 18.13:0. The Good CRC packet counter is a modulo 10,000
counter so values will always be between 0-9,999. A read of the register reads back the good CRC
packets and then clears the register so the subsequent reads will be 0 if no traffic has been received. If
traffic has been received since the last read, bit 15 will be set.
5.2
Copper PHY Error Counters
Idle errors = MII 10.7:0
RX errors = MII 19.7:0
False carrier = MII 20.7:0
Disconnects = MII 21.7:0
CRC errors = ExtMII 23.7:0
5.3
Near-End Loopback
When the near-end loopback test feature is enabled, the transmitted data is looped back in the PCS
block on the receive data signals. To enable the loopback, set register bit 0.14 to 1. Near-end loopback
mode involves traffic flow over the GMII/RGMII interface, so a breakout of the MAC interface on
SAMTEC connector J1 must be connected to another system for this mode to pass traffic.
5.4
Far-End Loopback
When the far-end loopback test feature is enabled, incoming data from a link partner on the Copper
interface to be transmitted back to the link partner on the Copper interface. To enable the loopback, set
register bit 23.3 to 1.
5.5
Transmitter Test Mode
1000BASE-T PMA test control can be configured through reg.9.15:13. Please refer to PMA Test
application note for additional information in regard to performing the PMA conformance test.