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VSC8502 Reference Board

VPPD-03822 VSC8502 User Guide Revision 1.0

8

5

Useful Test Features

5.1

Ethernet Packet Generator

ExtMII 29E is the Ethernet Packet Generator register. The EPG sends traffic in multiple of 10,000 frames 
regardless of when you stop transmit activity. Refer to the datasheet for configuration options.

A Good CRC packet counter is in ExtMII 18.13:0. The Good CRC packet counter is a modulo 10,000 
counter so values will always be between 0-9,999. A read of the register reads back the good CRC 
packets and then clears the register so the subsequent reads will be 0 if no traffic has been received. If 
traffic has been received since the last read, bit 15 will be set.

5.2

Copper PHY Error Counters

Idle errors = MII 10.7:0
RX errors = MII 19.7:0
False carrier = MII 20.7:0
Disconnects = MII 21.7:0
CRC errors = ExtMII 23.7:0

5.3

Near-End Loopback

When the near-end loopback test feature is enabled, the transmitted data is looped back in the PCS 
block on the receive data signals. To enable the loopback, set register bit 0.14 to 1. Near-end loopback 
mode involves traffic flow over the GMII/RGMII interface, so a breakout of the MAC interface on 
SAMTEC connector J1 must be connected to another system for this mode to pass traffic.

5.4

Far-End Loopback

When the far-end loopback test feature is enabled, incoming data from a link partner on the Copper 
interface to be transmitted back to the link partner on the Copper interface. To enable the loopback, set 
register bit 23.3 to 1.

5.5

Transmitter Test Mode

1000BASE-T PMA test control can be configured through reg.9.15:13. Please refer to PMA Test 
application note for additional information in regard to performing the PMA conformance test.

Содержание VSC8502

Страница 1: ...VSC8502 User Guide VSC8502 Reference Board May 2014...

Страница 2: ...5 Software Interface Microcontroller Card 3 3 6 Software Interface Microcontroller Card 4 4 Quick Start 5 4 1 Connecting the Power Supply 5 4 2 PC Software Installation 5 4 3 Connecting to the Board...

Страница 3: ...ory The revision history describes the changes that were implemented in this document The changes are listed by revision starting with the most current publication 1 1 Revision 1 0 Revision 1 0 of thi...

Страница 4: ...also optimizes power consumption in all link operating speeds and features Wake on LAN WOL power management using magic packets This document describes the architecture and usage of the VSC8502RD and...

Страница 5: ...tions Channel 1 Channel 0 GND GND GND GND GND GND GND GND GND GND GND GND RXD2 RXDV_CTL RXD0 RXD3 RXD1 RXCLK RXD3 RXDV_CTL RXD2 RXD0 RXD1 RXCLK TXD2 TXDV_CTL TXD0 TXD3 TXD1 TXCLK TXD3 TXDV_CTL TXD2 TX...

Страница 6: ...board there are three on board regulators that will convert the 5 V supplied by the PC to 1 0 V and 2 5 V for the VSC8502 and 3 3 V for other devices For the VSC8502RD VR board there is only one on bo...

Страница 7: ...the GUI by launching the setup exe file USB communication is assisted by the Silabs USBXpress drive If not present on the PC the user will need to download the USBXpress Development Kit from the Sili...

Страница 8: ...recommended to ensure correct performance over the greatest set of user scenarios for the PHY After initialization is performed refer to the PHY Datasheet section on Configuring the PHY and PHY Inter...

Страница 9: ...mmonly used speed advertisement definitions are as follows Table 2 Auto Negotiation Advertisements MII reg 4 bits 8 7 MII reg 4 bits 6 5 MII reg 9 bits 12 11 MII reg 9 bits 9 8 1000BT Master mode N A...

Страница 10: ...MII 19 7 0 False carrier MII 20 7 0 Disconnects MII 21 7 0 CRC errors ExtMII 23 7 0 5 3 Near End Loopback When the near end loopback test feature is enabled the transmitted data is looped back in the...

Страница 11: ...mine suitability of any products and to test and verify the same The information provided by Microsemi hereunder is provided as is where is and with all faults and the entire risk associated with such...

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