Key Components Description and Operation
UG0557 User Guide Revision 4.0
14
4.4
SerDes Interface
The SmartFusion2 Advanced Development Kit has x4 SerDes interfaces. The SerDes block can be
accessed using the PCIe edge connector, high-speed sub-miniature version-A (SMA) connectors, and/or
an on-board FPGA mezzanine card (FMC) low pin count (LPC) connector (J60).
Note:
All SerDes TXD pairs (SERDES0, SERDES1, SERDES2, and SERDES3) are capacitively coupled to the
SmartFusion2 device. Serial AC-coupling capacitors are used to provide common-mode voltage
independence.
For more information, see the Board Level Schematics document (provided separately).
4.4.1
SERDES0 Interface
The SERDES0 interface (Lane 0,1, 2, or 3) is directly routed to the PCIe connector. The SerDes
reference clocks are routed as follows.
•
SERDES0 reference clock 0 is directly routed from the PCIe connector to the SmartFusion2 device.
•
SERDES0 reference clock 1 is routed from the 100 MHz differential clock source (LVDS clock
oscillator) through resistors.
The following figure shows the SERDES0 interface of the SmartFusion2 Advanced Development Board.
Figure 7 •
SERDES0 Interface
Note:
Mount R977 and R978 to source the clock from 100 MHz differential oscillator to the SERDES0
REFCLK1.
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