Key Components Description and Operation
UG0557 User Guide Revision 4.0
21
The following figure shows the system reset interface of the SmartFusion2 Advanced Development
Board.
Figure 14 • System Reset Interface
For more information, see the Board Level Schematics document (provided separately).
4.10
Clock Sources
This section provides information about the clock sources available in the SmartFusion2 Advanced
Development Kit.
4.10.1
50 MHz Clock Oscillator
A 50 MHz clock oscillator with an accuracy of +/-50 ppm is available on the board. This clock oscillator is
connected to the FPGA fabric to provide a system reference clock.
An on-chip SmartFusion2 PLL can be configured to generate a wide range of high-precision clock
frequencies.
The following table provides package and pin details of the 50 MHz oscillator.
The following figure shows the 50 MHz clock oscillator interface.
Figure 15 • 50 MHz Clock Oscillator Interface
For more information, see the Board Level Schematics document (provided separately).
Table 8 •
50 MHz Clock
SmartFusion2 Advanced
Development Kit Pin Name
SmartFusion2 Package
Number
SmartFusion2 Device Pin Name
50MHZ_SECLK_B4_P1
P1
MSIO39PB4/CCC_NE0_CLKI1
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'(9567BQ
'6
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.
9
3XVKEXWWRQVZLWFK
6:
8
9''B5(*
5HVHW
06B567%
9
X)
8
6HQVH
736*'%95
5HVHW
0+]2VF
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*1'
75,67$7(
9''
287
9
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