Twister LX System Board Manual
Chapter 4: The BIOS Setup Utility
43
Passive Release
When enabled, CPU to PCI bus accesses are allowed
during passive release. Otherwise, the arbiter only ac-
cepts another PCI master access to local DRAM.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer
to support delay transaction cycles. Select Enabled to
support compliance with PCI specification version 2.1.
AGP Aperture Size (MB)
Select the size of the Accelerated Graphics Port (AGP)
aperture. The aperture is a portion of the PCI memory
address range dedicated for graphics memory address
space. Host cycles that hit the aperture range are for-
warded to the AGP without any translation.
SDRAM RAS-to-CAS Delay
This field lets you insert a timing delay between the CAS
and RAS strobe signals, used when DRAM is written to,
read from, or refreshed. Fast gives faster performance and
Slow gives more stable performance. This field applies
only when synchronous DRAM is installed in the system.
SDRAM RAS Precharge Time
If an insufficient number of cycles is allowed for the RAS
to accumulate its charge before DRAM refresh, the
refresh may be incomplete and the DRAM may fail to
retain data. This field applies only when synchronous
DRAM is installed in the system.
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of
clock cycles of CAS latency depends on the DRAM
timing. Do not reset this field from the default value
specified.
