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Twister LX System Board Manual
Chapter 4: The BIOS Setup Utility
42
CPU-To-PCI IDE Posting
Select Enabled to post write cycles from the CPU to the
PCI IDE interface. IDE accesses are posted in the CPU to
PCI buffers, for cycle optimization.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS
ROM at F0000h-FFFFFh, resulting in better system per-
formance. However, if any program writes to this memory
area, a system error may result.
Video BIOS Cacheable
Selecting Enabled allows caching of the video BIOS
ROM at C0000h to C7FFFh, resulting in better video
performance. However, if any program writes to this
memory area, a system error may result.
Video RAM Cacheable
Enable or disable the caching of the video RAM. The
default settings is Disabled.
8-Bit/16-Bit I/O Recovery Time
The I/O recovery mechanism adds bus clock cycles be-
tween PCI-originated I/O cycles to the ISA bus. This
delay takes place because the PCI bus is so much faster
than the ISA bus. These two fields let you add recovery
time (in bus clock cycles) for 16-bit and 8-bit I/O.
Memory Hole at 15M-16M
You can reserve this area of system memory for the ISA
adapter ROM. When this area is reserved, it cannot be
cached.