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Figure 5-8. System
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
Routing USB
Routing top or bottom
Max trace-length mismatch
between USB signals pairs
should be no greater than 3.8mm
90 ohms differential trace
impedance
SAMA5D2 System Pins
R&C
as close as possible
Top/Bot
Top/Bot
Top/Bot
Top/Bot
JTAG
USER BUTTON
WAKE UP
RESET
DIS BOOT
Clock sources
RevB
RXD
PIOBU0
ACN
PIOBU2
PIOBU4
PIOBU6
XIN
XOUT
PIOBU3
PIOBU5
XIN
XOUT
XIN32
XOUT32
ACP
ACN
PIOBU3
PIOBU2
PIOBU4
PIOBU5
ACP
RXD
XOUT32
XIN32
PIOBU1
PIOBU7
PIOBU0
PIOBU6
PIOBU1
PIOBU7
GND_POWER
GND_POWER
GND_POWER
GND_POWER
VDDBU
GNDUTMII
VDDANA
GND_POWER
GND_POWER
GND_POWER
VDD_3V3
VDD_3V3
GND_POWER
GND_POWER
VDDBU
USBA_DP
9
USBA_DM
9
USBB_DP
9
USBB_DM
9
NRST
3,8,11,12,13
SHDN
3
WKUP
8
DISABLE_BOOT
10
NRST
3,8,11,12,13
WKUP
8
NRST
3,8,11,12,13
HSIC_DATA
9
HSIC_STRB
9
CON_JTAG_Pin2
12
CON_JTAG_Pin4
12
CON_JTAG_Pin6
12
CON_JTAG_Pin8
12
RTCKIN
12
PA10_USER_BT
6
REV
DATE
MODIF.
DES.
DATE
VER.
SCALE
1/1
REV.
SHEET
INIT EDIT
A
A
RevA
8
13
B
XX-XXX-XX
ZhouB
XXX
08) SYSTEM
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XX
ZhouB 07-MAR-17
03-OCT-17
THR
X
X
-
X
X
X
-
X
X
X
X
X
B
REV
DATE
MODIF.
DES.
DATE
VER.
SCALE
1/1
REV.
SHEET
INIT EDIT
A
A
RevA
8
13
B
XX-XXX-XX
ZhouB
XXX
08) SYSTEM
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XX
ZhouB 07-MAR-17
03-OCT-17
THR
X
X
-
X
X
X
-
X
X
X
X
X
B
REV
DATE
MODIF.
DES.
DATE
VER.
SCALE
1/1
REV.
SHEET
INIT EDIT
A
A
RevA
8
13
B
XX-XXX-XX
ZhouB
XXX
08) SYSTEM
06-JAN-17
SAMA5D2-PTC-EK
XXX XX-XXX-XX
ZhouB 07-MAR-17
03-OCT-17
THR
X
X
-
X
X
X
-
X
X
X
X
X
B
R139
5.62K-1%
R0402
R132
0R
R0402
R122
DNP
R0402
R146
100R-1%
r0402
R127
330R R0402
R130
330R R0402
R135
10K
R0402
R124
330R R0402
R144
0R
R0402
BP3
Tact Switch
FSM2JSML
R134
0R
R0402
R129
330R R0402
C98
20pF
C0402
R140
100K
R0402
C97
20pF
C0402
R131
0R
R0402
R133
DNP
R0402
R147
100R-1%
r0402
ATSAMA5D27C-CN
U6F
bga289p8
ADVREFP
M6
CLK_AUDIO
U3
ACN
T1
ACP
U1
HHSDMA
R8
HHSDMB
U9
HSIC_STRB
U10
HHSDPA
T8
HHSDPB
U8
HSIC_DATA
T9
JTAGSEL
T2
NRST
U2
PIOBU0
R3
PIOBU1
N8
PIOBU2
R2
PIOBU3
R5
PIOBU4
R4
PIOBU5
P5
PIOBU6
P6
PIOBU7
M8
RXD
N4
SDCAL
T10
SHDN
R1
TST
P3
VBG
R6
WKUP
P4
XIN
U7
XIN32
P1
XOUT
U6
XOUT32
P2
R238
10K
R0402
BP1
Tact Switch
FSM2JSML
R236
10K
R0402
R142
100K
R0402
R123
DNP
R0402
C100
22pF
C0402
R143
100R-1% R0402
BP2
Tact Switch
FSM2JSML
R141
100K
R0402
R125
330R R0402
C96
20pF
C0402
C101
100nF
C0402
JP7
DNP
1
2
R136
20K-1%
R0402
R137
0R
R0402
R138
DNP
R0402
Y1
24MHz CL=10pF
x4s32x25
1
4
3
2
J1
DNP
FTSH-105-01-F-DV-P-TR
1
2
3
4
5
6
7
8
9
10
R126
330R R0402
C99
20pF
C0402
C102
10pF
C0402
R128
0R
R0402
R145
100R-1%
r0402
Y2
32.768KHz CL=12.5pF
X4S70X15
1
2
3
4
J2
Header 2X5
FTSH-105-01-F-DV-P-TR
1
2
3
4
5
6
7
8
9
10
BP4
Tact Switch
FSM2JSML
SAMA5D2-PTC-EK
Appendix A. Schematics and Layouts
©
2017 Microchip Technology Inc.
DS50002709A-page 56