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Table 3-4. NAND Flash Signal Descriptions
PIO
Mnemonic
Shared PIO
Signal Description
PA22
NAND_D0
SDMMC1-QSPI
Data 0
PA23
NAND_D1
QSPI
Data 1
PA24
NAND_D2
QSPI
Data 2
PA25
NAND_D3
QSPI
Data 3
PA26
NAND_D4
QSPI
Data 4
PA27
NAND_D5
QSPI
Data 5
PA28
NAND_D6
SDMMC1
Data 6
PA29
NAND_D7
–
Data 7
PA30
NANDWE
SDMMC1
–
PA31
NCS3
–
Chip Select
PB00
NANDALE
–
–
PB01
NANDCLE
–
–
PB02
NANDOE
–
–
PC08
NANRDY
–
–
3.2.7.5
NAND Flash CS Disable
On-board jumper JP8 controls the selection (CS#) of the NAND Flash memory.
3.2.8
Additional Memories
3.2.8.1
Serial Flash
The SAMA5D2 includes two high-speed Serial Peripheral Interface (SPI) controllers. The SPI is a full
duplex synchronous bus supporting a single master and multiple slave devices. The SPI bus consists of
the following items:
•
a serial clock line (generated by the master)
•
a data output line from the master
•
a data input line to the master
•
one or more active low chip select signals (output from the master)
One SPI port is used to interface with the on-board serial Flash.
The following figure illustrates the implementation of an SPI Flash memory.
Figure 3-17. Serial Flash
SPI0_CS0_PA17
GND_POWER
VDD_3V3
SPI0_MOSI_PA15
SPI0_MISO_PA16
SPI0_SPCK_PA14
C119
100nF
C0402
U16
SST26VF032B-104I/SM
soic8jg
HOLD
7
GND
4
VCC
8
CS
1
SCK
6
SI
5
SO
2
WP
3
SAMA5D2-PTC-EK
Board Components
©
2017 Microchip Technology Inc.
DS50002709A-page 18