Note:
The serial Flash is optional and not mounted on board.
3.2.8.2
QSPI Serial Flash
The SAMA5D2 provides two Quad Serial Peripheral Interfaces (QSPI).
A QSPI is a synchronous serial data link that provides communication with external devices in Master
mode.
The QSPI can be used in SPI mode to interface with serial peripherals (such as ADCs, DACs, LCD
controllers, CAN controllers and sensors), or in Serial Memory mode to interface with serial Flash
memories.
The QSPI allows the system to execute code directly from a serial Flash memory (XIP, or Execute In
place, technology) without code shadowing to RAM. The serial Flash memory mapping is seen in the
system as other memories (ROM, SRAM, DRAM, etc.).
With the support of the Quad SPI protocol, the QSPI allows the system to use high-performance serial
Flash memories which are small and inexpensive, instead of larger and more expensive parallel Flash
memories.
The figure below illustrates the implementation of a QSPI Flash memory.
Figure 3-18. QSPI Serial Flash
QSPI0_CS_PA23
VDD_3V3
GND_POWER
VDD_3V3
VDD_3V3
QSPI0_IO0_PA24
QSPI0_IO1_PA25
QSPI0_IO2_PA26
QSPI0_IO3_PA27
QSPI0_SCK_PA22
U14
SST26VF064B-104I/SM
soic8jg
SI/SIO0
5
SO/SIO1
2
SIO2
3
SIO3
7
SCLK
6
CS#
1
GND
4
VCC
8
C120
100nF
C0402
R186
10K
R0402
R187
10K
R0402
JP13
Header 1X2
1 2
R242
10K
A jumper (JP13) is used to disable the QSPI Flash.
Table 3-5. SPI and QSPI Signal Descriptions
PIO
Mnemonic
PIO Shared
Signal Description
PA14
SPI0_SPCK
_
SPI clock
PA15
SPI0_MOSI
_
Master out - Slave in
PA16
SPI0_MISO
_
Master in - Slave out
PA17
SPI0_NPCS0
_
Chip select
_
_
_
_
PA22
QSPI0_SCK
SDMMC1-Nand Flash
QSPI clock
PA23
QSPI0_CS
Nand Flash
Chip select
PA24
QSPI0_IO0
Nand Flash
Data0
PA25
QSPI0_IO1
Nand Flash
Data1
SAMA5D2-PTC-EK
Board Components
©
2017 Microchip Technology Inc.
DS50002709A-page 19
