Microchip Technology PL485-EK, Руководство пользователя

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Figure 3-34. JLINK Debugger Schematic
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B B
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PL485 - Evaluation Kit
03/03/2020 18:10:13
JLINK debugger.SchDoc
Project Title
Sch #: Date:
File:
Revision: Sheet
Designed with
Drawn By:
JLCF
Sheet Title
JLINK debugger
Engineer:
JLCF
03-PL485
1
Size A3
PL485-EK
PartNumber:
Variant Name
CEN-B
Altium.com
ATSAM3U4CA-CU
V
D
D
A
N
A
K
2
ADVREF
J3
G
N
D
A
N
A
K
3
AD12BVREF
K4
PA22/PGMD14
H4
PA30
J4
P
B
3
J5
P
B
4
K
5
V
D
D
C
O
R
E
_3
E
7
PA13/PGMD5
H5
G
N
D
2
F
6
PA15/PGMD7
H6
PA16/PGMD8
J6
PA17/PGMD9
K7
P
B
16
F
7
P
B
15
G
7
PA18/PGMD10
H7
PA19/PGMD11
J7
PA20/PGMD12
K8
PA21/PGMD13
J8
PA23/PGMD15
K9
XIN32
A10
PA24
H8
PA25
K10
PA26
J9
PA0/PGMNCMD
J10
PA1/PGMRDY
H9
PA2/PGMNOE
H10
PA3/PGMNVALID
G8
PA4/PGMM0
G10
PA5/PGMM1
G9
PA6/PGMM2
F8
NRST
B7
V
D
D
C
O
R
E
_4
H
1
G
N
D
1
E
2
V
D
D
IO
_3
E
6
V
D
D
C
O
R
E
_5
G
5
DFSDM
D1
G
N
D
3
G
6
V
D
D
U
T
M
I
B
3
V
D
D
IN
A
8
FWUP
D8
ERASE
D6
TEST
D7
XIN
A2
XOUT32
B10
TDI
B9
V
D
D
O
U
T
A
9
PA12/PGMD4
D10
TDO/TRACESWO
B8
TMS/SWDIO
C7
TCK/SWCLK
A7
PA7/PGMM3
F10
P
B
24
B
6
PA8/PGMD0
E10
V
D
D
IO
_2
F
5
PA14/PGMD6
K6
P
B
23
A
6
P
B
22
C
6
P
B
14
C
4
P
B
10
B
4
P
B
9
E
4
G
N
D
P
L
L
C
3
P
B
8
J2
P
B
7
K
1
P
B
6
J1
P
B
13
G
4
P
B
12
F
2
P
B
11
G
1
P
B
2
G
2
P
B
1
F
1
P
B
0
G
3
PA10/PGMD2
E8
V
D
D
IO
_1
F
3
V
D
D
C
O
R
E
_1
B
1
PA31
F4
PA29
E1
PA28
E3
V
D
D
C
O
R
E
_2
D
4
G
N
D
U
T
M
I
B
2
DFSDP
C1
DHSDM
D2
DHSDP
C2
NRSTB
C8
XOUT
A3
V
D
D
P
L
L
D
3
PA11/PGMD3
D9
PA9/PGMD1
E9
P
B
20
D
5
P
B
19
C
5
P
B
18
B
5
P
B
17
A
4
P
B
5
H
2
PA27
H3
P
B
21
A
5
V
D
D
B
U
C
10
G
N
D
B
U
E
5
VBG
A1
JTAGSEL
C9
V
D
D
C
O
R
E
_6
F
9
U5
A
T
S
A
M
3
U
4
C
A
-C
U
T
F
B
G
A
-1
0
0
GND
3V3_3U
2.2uF
16V
0603
C106
0.1uF
10V
0402
C96
2.2uF
16V
0603
C107
0.1uF
10V
0402
C108
VBUS_JLINK
STB
1
GND
2
OUT
3
VDD
4
12.00 MHz
DSC6011JI1A-012.0000
Y4
EP
7
VIN
6
VOUT
1
GND
3
EN
4
NC
5
VOUT
2
MIC5528 3V3
U7
XIN_SAM3 51R
0402 1%
R94
GND GND
3V3_3U
GND GND GND GND
0.1uF
10V
0402
C92
4.7uF
10V
0402
C91
0.1uF
10V
0402
C89
0.1uF
10V
0402
C99
0.1uF
10V
0402
C100
0.1uF
10V
0402
C104
0.1uF
10V
0402
C98
0.1uF
10V
0402
C102
0.1uF
10V
0402
C94
0.1uF
10V
0402
C93
4.7uF
10V
0402
C97
0.1uF
10V
0402
C90
0.1uF
10V
0402
C88
0.1uF
10V
0402
C101
0.1uF
10V
0402
C105
0.1uF
10V
0402
C103
0.1uF
10V
0402
C95
3V3_3U
3V3_3U 3V3_3U VDD_CORE_3U
VDD_CORE_3U GND
GND
0.1uF
10V 0402
C83
NC
1
1OE
2
1Y
4
1A
3
2OE
5
2Y
7
2A
6
3Y
10
3A
11
NC
9
4Y
13
3OE
12
GND
8
4A
14
4OE
15
VCC
16
IDTQS3VH125
U6
JTAG_CONN_nRST
JTAG_CONN_TDI
JTAG_CONN_TMS
JTAG_CONN_TCK
JTAG_CONN_TDO
S
1
I0A
2
I1A
3
YA
4
I0B
5
I1B
6
YB
7
GND
8
YC
9
I1C
10
I0C
11
YD
12
I1D
13
I0D
14
E
15
VCC
16
IDTQS3VH257PAG
U4
100k 0402 5%
R70
3
1
2
BSS138N
Q4
DIS_JLINK
JLINK_TCK_IN
JLINK_TDI_IN
JLINK_TDO_IN
JLINK_TMS_IN
JLINK_nRST
100R 0402
1%
R79
NRST
JTAG_nRST
3V3
3V3
JTAG_CONN_TDI
JTAG_CONN_TMS
JTAG_CONN_TCK
JTAG_CONN_TDO
JTAG_CONN_nRST
ENSPI
TRESIN
TRESOUT
JLINK_UART_RX
JLINK_UART_TX
JLINK_TDI_IN
JLINK_TMS_IN
ENSPI
LED1_3U
LED2_3U
DIS_CDC
DIS_JLINK
JLINK_TDO_IN
JLINK_TCK_IN
150R
R82
150R
R81
150R
R80
2 1
4 3
GREEN
RED
0805
D22
1k
0402 5%
R88
1k
0402 5%
R89
3V3_3U
150R R73
100R 0402
1%
R72
JLINK_nRST
JLINK OBD
GND
GND GND
0.1uF
10V 0402
C84
GND
DIS_JLINK
10k
0402
1%
R85
DIS_CDC
10k
0402
1%
R84
1
2
HDR-2.54 Male 1x2
J14
1
2
HDR-2.54 Male 1x2
J13
JP1 JP2
3V3_3U 3V3_3U
GND GND
0.01uF
50V
0402
C85
1N4148 D21
6.8k 0402 1%
R78
10k
0402 1%
R77
10pF 50V 0402 C86
0.01uF
50V
0402
C87
BOT TOP
Side
Side
1 2
3 4
7 8
9 10
11 12
13
15 14
16
J11
pads on PCB
NRST_3U
TDI_3U
TDO_3U
TCK_3U
TMS_3U
1
2
HDR-2.54 Male 1x2
J10
100R
0402
1%
R74
100R
0402
1%
R75
GND
GND
3V3_3U
3V3_3U
GND GND
3V3_3U
3V3_3U
3V3_3U
GND
XIN_SAM3
100k 0402 5% R83
3V3_3U
39R 0402 1%
R86
39R 0402 1% R87
EARTH0
VBUS_JLINK
JLINK_USBHS_N
JLINK_USBHS_P
120R
BLM18PG121SN1D
FB13
DIFF90
GND
B2
1
GND
2
VCCA
3
A2
4
A1
5
OE
6
VCCB
7
B1
8
TXS0102 U8
22R 0402 1% R96
22R 0402 1% R98
0.1uF
10V
0402
C109
0.1uF
10V
0402
C110
DIS_CDC
JLINK_UART_TX
JLINK_UART_RX
0R 0402 R97
0R 0402
R99
GND GND
3V3_3U 3V3
Connector for JTAG/SWD progr ammer /debugger
3V3
GND
3V3
1
2
3 4
5
6
7 8
9
10
J15
nRESET
VCC
GND
GND
KEY
GNDDetect
PB[0..14]
PB
2
PB
3
PB
4
PB
5
PB
6
PB
8
PB
7
PB
9
PB
10
PB
1
PB
12
PB
11
PB
13
PB
14
PB[0..14]
PB
0
PB6
PB7
PB5
PB4
100R R95
PB11
PB10
TDI/NC
TDO/SWO
TCK/SWCLK
TMS/SWDIO
DBGU_TX
DBGU_RX
JLINK debugger
JLINK_USBFS_N
JLINK_USBFS_P
TDI/NC
TDO/SWO
TCK/SWCLK
TMS/SWDIO
Disable CDC Disable J LINK
1
2
3
4
5
0
ID
D
+
D
-+
5V
G
N
D
USB2.0 MICRO-B FEMALE
J12
JLINK/JTAG
0R 0402
R76
10
0k
R
9
0
10
0k
R
9
1
10
0k
R
9
2
10
0k
R
9
3
TRSTIN
TRSTOUT
150R
R71
FD7
FD8
TP22
90Ω ±10% differential trace impedance
Routing top or bottom
3.8 PL485-EK Layout
This section contains the layout graphics for the PL485-EK board:
• Layer 1: Top Layer, Figure 3-35
• Layer 2: Mid Layer 1 (Ground), Figure 3-36
• Layer 3: Mid Layer 2 (Power Supplies), Figure 3-37
• Layer 4: Bottom Layer, Figure 3-38
• Top Components Placement, Figure 3-39
• Bottom Components Placement, Figure 3-40
PL485-EK
PL485-EK Board
©
2020 Microchip Technology Inc.
User Guide
DS50002954B-page 32