Figure 3-30. PL485 Schematic
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PL485 - Evaluation Kit
03/03/2020 18:10:11
PL485.SchDoc
Project Title
Sch #:
Date:
File:
Revision:
Sheet
Designed with
Drawn By:
JLCF
Sheet Title
PL485
Engineer:
JLCF
03-PL485
1
Size A3
PL485-EK
PartNumber:
Variant Name
CEN-B
Altium.com
PL485
PA0
H1
PA1
K1
PA2
H2
PA3
J2
PA4
J1
PA5
K2
PA6
L3
PA7/XIN32
J3
PA8/XOUT32
K3
PA9
G9
PA10
H11
PA11
H10
PA12
J11
PA13
J10
PA14
J9
PA15
L4
PA16
K4
PA17
J8
PA18
K8
PA19
H8
PA20
K9
PA21/DM
L6
PA22/DP
K6
PA23
L5
PA24
F5
PA25
F3
PA26
F6
PA27
F8
PA28
F7
PA29
G5
PA30
G7
PA31
F1
MPL485A-I/AJA
U1A
PB0
K10
PB1
L8
PB2
L9
PB3
K11
PB4
G2
PB5
G10
PB6
F10
PB7
F9
PB8/XOUT
G11
PB9/XIN
F11
PB10
G8
PB11
H9
PB12
J4
PB13
F4
PB14
G1
PB15
F2
MPL485A-I/AJA
U1B
ADVREF
K7
MCU_TST
H4
MCU_NRST
H3
JTAGSEL
G3
MPL485A-I/AJA
U1C
PL_VZC
A2
PL_PA1
A3
PL_PA2/TRACESWO
D3
PL_PA3
E6
PL_PA4/SWDIO
D2
PL_PA5/SWCLK
E2
PL_PA0
E5
PL_PA6/NPCS0
G6
PL_PA7/SPCK
G4
PL_PA8/MOSI
E7
PL_PA9/MISO
E8
PL_XIN
B2
PL_XOUT
B1
PL_AGC
B9
PL_TXRX1
A10
PL_TXRX0
A9
PL_EMIT3
C10
PL_EMIT2
C11
PL_EMIT1
D10
PL_EMIT0
D11
PL_VIN
A7
PL_VREFP
B7
PL_VREFN
B6
PL_VREFC
A6
PL_NRST
D4
PL_TST
E3
PL_LDO_ENABLE
E4
MPL485A-I/AJA
U1D
NRST
ADVREF
PA[0..31]
PB[0..14]
3V3
PL_TST
PL_TXRX0
PL_TXRX1
PL_VZC
PL_AGC
PL_VIN
PL_TXRX0
PL_TXRX1
PL_AGC
PL_VIN
PL_VZC
PL_EMIT[0..3]
PLC Coupling
PL_TXRX0
PL_TXRX1
PL_AGC
PL_VIN
PL_VZC
PLC_Coupling
PA0
PA1
PA2
PA3
PA4
PA5
PA7
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA8
PA16
PA19
PA20
PA23
PB0
PB1
PB3
PB4
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB14
PB5
PA6
PA17
PA18
PA31
PB2
PA7
PA8
32.768Khz
Y3
GND
GND
GND
GND
PB8
PB9
Clext = 2x (Ccrystal - Cintload - Cpcb)
Clext = 2x (12.5/17.5 - 7.5/9/10.5 - x)
Clext = 2x (16 - 9 - 1)
Clext = 12 pF
Pag. 1061
Clext = 2x (Ccrystal - Cpara - Cpcb)
Clext = 2x (12.5 - 0.5 - x)
Clext = 2x (12.5 - 0.5 - 1)
Clext = 22 pF (<24 pF Max)
Pag. 1059
GND
12pF
50V
0402
C31
12pF
50V
0402
C30
22pF
50v
0603
C47
22pF
50v
0603
C46
PL_LDO_EN
GND
GND
Clext = 2x (Ccrystal - Cpara- Cpcb)
Clext = 2x (4/18 - 0.6/0.7/0.8 - x)
Clext = 2x (18 - 0.7 - 1)
Clext = 33 pF
Pag. 41
GND
PL_XIN
PL_XOUT
PL_XOUT
PL_XIN
AGND
10000pF
C1
0.022uF
C4
0.022uF
C2
1
3
24MHz
Y2
33pF
50V
0402
C33
33pF
50V
0402
C32
PA[0..31]
PB[0..14]
NRST
DUSB_N
DUSB_P
DUSB_N
DUSB_P
PL_NRST
USB_DP
USB_DN
USB Device
USB_Device
0R
0603
R3
0R
0603
R1
PL_CD
PL_EXTIN
PL_NPCS0
PL_SPCK
PL_MOSI
PL_MISO
1
2
J1
PB12
MCU 20MHz clock
MCU slow clock
PLC 24MHz clock
(MCU Erase)
MCU ERASE
VDDIO
H5
VDDIO
A4
VDDIO
B4
VDDIN_AN
A5
VDDIN_AN
B8
GND
A1
VDDIO
B10
PL_VDDCORE
B11
VDDPLL
C1
VDDPLL
C2
PL_VDDCORE
D1
VDDIN
E1
VDDIO
E9
VDDIO
E11
VDDIO
D9
VDDIO
E10
GND
A11
GND
C4
GND
C5
GND
C7
GND
C8
GND
C9
GND
D5
GND
D6
GND
D7
GND
D8
GND
H6
GND
H7
GND
J6
GND
L1
GND
L11
GND
B3
GND
C3
AGND
B5
AGND
C6
AGND
A8
VDDIO
J5
VDDIO
K5
MCU_VDDCORE
L2
MCU_VDDCORE
L10
VDDOUT
L7
VDDUSB
J7
MPL485A-I/AJA
U1E
GND
3V3
MCU_VDDCORE
AGND
3V3A
FD5
FD6
GND
3V3
0R
R4
0R
R5
GND
AGND
470R
FB2
3V3
4.
7u
F
C
3
5
3V3A
AGND
GND
4.
7u
F
C
3
8
GND
470R
FB1
VDDPLL
PL_VDDCORE
PL_VDDCORE_DEC
Connected to ball D1
Connected to ball B11
GND
MCU_VDDCORE
GND
Near ball L7
PL_VDDCORE_DEC
VDDPLL
PL485 Decoupling
TP2
TP1
GND
1
4
2
3
TL3301NF260QG
SW1
GND
NRST
MCU Reset
PL_CD
PL_EXTIN
PL_MISO
PL_MOSI
PL_SPCK
PL_NPCS0
PL_NRST
PL_TST
PL_LDO_EN
MCU
PLC
POWER PL485
PL_VDDCORE
1u
F
C
5
4.
7u
F
C
1
0
1u
F
C
7
4.
7u
F
C
11
4.
7u
F
C
1
2
4.
7u
F
C
1
3
4.
7u
F
C
1
4
4.
7u
F
C
1
5
Near balls E9
E10-E11-D9
3V3
Near ball J5
Near ball A4
4.
7u
F
C
2
7
4.
7u
F
C
2
6
Near balls E1-J7
3V3
GND
3V3
10000pF
C3
2.
2u
F
C
4
3
2.
2u
F
C
4
1
0.
1u
F
C
6
0.
1u
F
C
8
0.
1u
F
C
9
0.
1u
F
C
1
6
0.
1u
F
C
1
7
0.
1u
F
C
1
8
0.
1u
F
C
1
9
0.
1u
F
C
2
0
0.
1u
F
C
2
1
0.
1u
F
C
2
2
0.
1u
F
C
2
3
0.
1u
F
C
2
4
0.
1u
F
C
2
5
0.
1u
F
C
2
8
0.
1u
F
C
2
9
0.
1u
F
C
3
9
0.
1u
F
C
4
0
0.
1u
F
C
4
2
0.
1u
F
C
4
4
0.1uF
C48
0R 0402
R2
0R 0402
R7
10k
R8
0.
1u
F
C
3
6
0.
1u
F
C
3
7
0.1uF
25V
0402
C34
GND
ADVREF
GND
3V3
1R
0402
1%
R6
4.7uF
10V
0402
C45
10uH
L1
Near ball K7
1
3
20MHz
Y1
PL_EMIT3
PL_EMIT3
PL_EMIT3
PL_EMIT3
PL_EMIT[0..3]
PL_EMIT[0..3]
PL485-EK
PL485-EK Board
©
2020 Microchip Technology Inc.
User Guide
DS50002954B-page 28