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Microchip Technology PIC12F1501 Скачать руководство пользователя страница 222

 2011-2015 Microchip Technology Inc.

DS40001609E-page 223

PIC16(L)F1508/9

22.0

ENHANCED UNIVERSAL 
SYNCHRONOUS 
ASYNCHRONOUS RECEIVER 
TRANSMITTER (EUSART)

The Enhanced

 

Universal Synchronous Asynchronous

Receiver Transmitter

 

(EUSART) module is a serial I/O

communications peripheral. It contains all the clock
generators, shift registers and data buffers necessary
to perform an input or output serial data transfer
independent of device program execution. The
EUSART, also known as a Serial Communications
Interface (SCI), can be configured as a full-duplex
asynchronous system or half-duplex synchronous
system. Full-Duplex mode is useful for
communications with peripheral systems, such as CRT
terminals and personal computers. Half-Duplex
Synchronous mode is intended for communications
with peripheral devices, such as A/D or D/A integrated
circuits, serial EEPROMs or other microcontrollers.
These devices typically do not have internal clocks for
baud rate generation and require the external clock
signal provided by a master synchronous device.

The EUSART module includes the following capabilities:
• Full-duplex asynchronous transmit and receive
• Two-character input buffer
• One-character output buffer
• Programmable 8-bit or 9-bit character length
• Address detection in 9-bit mode
• Input buffer overrun error detection
• Received character framing error detection
• Half-duplex synchronous master
• Half-duplex synchronous slave
• Programmable clock polarity in synchronous 

modes

• Sleep operation
The EUSART module implements the following
additional features, making it ideally suited for use in
Local Interconnect Network (LIN) bus systems:
• Automatic detection and calibration of the baud rate
• Wake-up on Break reception
• 13-bit Break character transmit
Block diagrams of the EUSART transmitter and
receiver are shown in 

Figure 22-1

 and 

Figure 22-2

.

The EUSART transmit output (TX_out) is available to
the TX/CK pin and internally to the following peripherals:
• Configurable Logic Cell (CLC)

FIGURE 22-1:

EUSART TRANSMIT BLOCK DIAGRAM      

TXREG register

8

Pin Buffer 

and Control

TXIF

TRMT

TX9D

Data bus

8

TXIE

Interrupt

TX/CK

TX_out

TX9

TXEN

Transmit Shift Register (TSR)

(8)

0

MSb

LSb

÷ n

Multiplier

x4

SYNC

BRGH

BRG16

x16

x64

1

1

1

1

1

x

x

x 0

0

0

0

0

0

0

n

+ 1

SPBRGH SPBRGL

Baud Rate Generator

F

OSC

BRG16

Rev. 10-000113A

10/14/2013

Содержание PIC12F1501

Страница 1: ...ar Program Memory Addressing Up to 512 bytes Linear Data Memory Addressing High Endurance Flash Data Memory HEF 128 bytes if nonvolatile data storage 100k erase write cycles eXtreme Low Power XLP Feat...

Страница 2: ...input sources PWM CLC NCO PIC12 L F1501 PIC16 L F150X FAMILY TYPES Device Data Sheet Index Program Memory Flash words Data SRAM bytes I O s 2 10 bit ADC ch Comparators DAC Timers 8 16 bit PWM EUSART...

Страница 3: ...e 1 for location of all peripheral functions 18 17 16 15 20 19 RC6 RC7 RB7 RB4 RB5 RB6 20 pin PDIP SOIC SSOP PIC16 L F1508 PIC16 L F1509 Note 1 See Table 1 for location of all peripheral functions 2 I...

Страница 4: ...FLT CLC1 PWM3 INT IOC Y RA3 4 1 T1G 1 SS 1 CLC1IN0 IOC Y MCLR VPP RA4 3 20 AN3 SOSCO T1G IOC Y CLKOUT OSC2 RA5 2 19 SOSCI T1CKI NCO1CLK IOC Y CLKIN OSC1 RB4 13 10 AN10 SDA SDI CLC3IN0 IOC Y RB5 12 9 A...

Страница 5: ...tor Module 145 18 0 Timer0 Module 152 19 0 Timer1 Module with Gate Control 155 20 0 Timer2 Module 166 21 0 Master Synchronous Serial Port MSSP Module 169 22 0 Enhanced Universal Synchronous Asynchrono...

Страница 6: ...determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page The last character of the literature number is the version number e g DS30000A...

Страница 7: ...al PIC12 L F1501 PIC16 L F1503 PIC16 L F1507 PIC16 L F1508 PIC16 L F1509 Analog to Digital Converter ADC Complementary Wave Generator CWG Digital to Analog Converter DAC Enhanced Universal Synchronous...

Страница 8: ...ing Generation INTRC Oscillator MCLR Program Flash Memory FVR DAC ADC 10 bit Temp Indicator C1 C2 TMR0 TMR1 TMR2 MSSP1 PWM1 EUSART PWM2 PWM3 PWM4 CLC1 CLC2 CLC3 CLC4 NCO1 CWG1 PORTA PORTB PORTC Rev 10...

Страница 9: ...er0 clock input INT ST External interrupt PWM3 CMOS PWM output CLC1 CMOS Configurable Logic Cell source output CWG1FLT ST Complementary Waveform Generator Fault input RA3 CLC1IN0 VPP T1G 1 SS 1 MCLR R...

Страница 10: ...C1IN1 AN Comparator negative input C2IN1 AN Comparator negative input PWM4 CMOS PWM output NCO1 CMOS Numerically Controlled Oscillator is source output RC2 AN6 C1IN2 C2IN2 RC2 TTL CMOS General purpose...

Страница 11: ...elect input RC7 AN9 CLC1IN1 SDO RC7 TTL CMOS General purpose I O AN9 AN ADC Channel input CLC1IN1 ST Configurable Logic Cell source input SDO CMOS SPI data output VDD VDD Power Positive supply VSS VSS...

Страница 12: ...bility to read program and data memory Automatic Interrupt Context Saving 16 level Stack with Overflow and Underflow File Select Registers Instruction Set FIGURE 2 1 CORE BLOCK DIAGRAM 15 15 15 15 8 8...

Страница 13: ...ause a soft ware Reset See Section 3 5 Stack for more details 2 3 File Select Registers There are two 16 bit File Select Registers FSR FSRs can access all file registers and program mem ory which allo...

Страница 14: ...the implemented memory space The Reset vector is at 0000h and the interrupt vector is at 0004h See Figure 3 1 3 2 High Endurance Flash This device has a 128 byte section of high endurance program Fla...

Страница 15: ...04h 0005h 07FFh 0800h 0FFFh 1000h 7FFFh CALL CALLW RETURN RETLW Interrupt RETFIE On chip Program Memory 15 Rev 10 000040A 7 30 2013 PIC16 L F1508 CALL CALLW RETURN RETLW Interrupt RETFIE On chip Progr...

Страница 16: ...SRxH register and reading the match ing INDFx register The MOVIW instruction will place the lower eight bits of the addressed word in the W register Writes to the program memory cannot be performed vi...

Страница 17: ...rs FSR See Section 3 6 Indirect Addressing for more information Data memory uses a 12 bit address The upper five bits of the address define the Bank address and the lower seven bits select the registe...

Страница 18: ...REGISTER 3 1 STATUS STATUS REGISTER U 0 U 0 U 0 R 1 q R 1 q R W 0 u R W 0 u R W 0 u TO PD Z DC 1 C 1 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 u Bit is unchanged x...

Страница 19: ...M There are up to 80 bytes of GPR in each data memory bank The Special Function Registers occupy the 20 bytes after the core registers of every data memory bank addresses x0Ch x8Ch through x1Fh x9Fh 3...

Страница 20: ...BP 015h TMR0 095h OPTION_REG 115h CMOUT 195h PMCON1 215h SSP1CON1 295h 315h 395h IOCBN 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h 316h 396h IOCBF 017h TMR1H 097h WDTCON 117h FVRCO...

Страница 21: ...ON1 215h SSP1CON1 295h 315h 395h IOCBN 016h TMR1L 096h PCON 116h BORCON 196h PMCON2 216h SSP1CON2 296h 316h 396h IOCBF 017h TMR1H 097h WDTCON 117h FVRCON 197h VREGCON 217h SSP1CON3 297h 317h 397h 018h...

Страница 22: ...h 71Ch 79Ch 41Dh 49Dh 51Dh 59Dh 61Dh 69Dh 71Dh 79Dh 41Eh 49Eh NCO1CON 51Eh 59Eh 61Eh 69Eh 71Eh 79Eh 41Fh 49Fh NCO1CLK 51Fh 59Fh 61Fh 69Fh 71Fh 79Fh 420h Unimplemented Read as 0 4A0h Unimplemented Read...

Страница 23: ...D91h E11h E91h F11h F91h C12h C92h D12h D92h E12h E92h F12h F92h C13h C93h D13h D93h E13h E93h F13h F93h C14h C94h D14h D94h E14h E94h F14h F94h C15h C95h D15h D95h E15h E95h F15h F95h C16h C96h D16h...

Страница 24: ...LS1 F1Eh CLC2GLS2 F1Fh CLC2GLS3 F20h CLC3CON F21h CLC3POL F22h CLC3SEL0 F23h CLC3SEL1 F24h CLC3GLS0 F25h CLC3GLS1 F26h CLC3GLS2 F27h CLC3GLS3 F28h CLC4CON F29h CLC4POL F2Ah CLC4SEL0 F2Bh CLC4SEL1 F2Ch...

Страница 25: ...am Counter PC Least Significant Byte 0000 0000 0000 0000 x03h or x83h STATUS TO PD Z DC C 1 1000 q quuu x04h or x84h FSR0L Indirect Data Memory Address 0 Low Pointer 0000 0000 uuuu uuuu x05h or x85h F...

Страница 26: ...Period Register 1111 1111 1111 1111 01Ch T2CON T2OUTPS 3 0 TMR2ON T2CKPS 1 0 000 0000 000 0000 01Dh to 01Fh Unimplemented Bank 1 08Ch TRISA TRISA5 TRISA4 2 TRISA2 TRISA1 TRISA0 11 1111 11 1111 08Dh TR...

Страница 27: ...2 Flash Program Memory Address Register High Byte 1000 0000 1000 0000 193h PMDATL Flash Program Memory Read Data Register Low Byte xxxx xxxx uuuu uuuu 194h PMDATH Flash Program Memory Read Data Regis...

Страница 28: ...3h IOCAF IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 00 0000 00 0000 394h IOCBP IOCBP7 IOCBP6 IOCBP5 IOCBP4 0000 0000 395h IOCBN IOCBN7 IOCBN6 IOCBN5 IOCBN4 0000 0000 396h IOCBF IOCBF7 IOCBF6 IOCBF5 IOC...

Страница 29: ...PWM4DCH 7 0 xxxx xxxx uuuu uuuu 61Ch PWM4CON0 PWM4EN PWM4OE PWM4OUT PWM4POL 0000 0000 61Dh to 61Fh Unimplemented Bank 13 68Ch to 690h Unimplemented 691h CWG1DBR CWG1DBR 5 0 00 0000 00 0000 692h CWG1DB...

Страница 30: ...OL LC3G3POL LC3G2POL LC3G1POL 0 xxxx 0 uuuu F22h CLC3SEL0 LC3D2S 2 0 LC3D1S 2 0 xxx xxx uuu uuu F23h CLC3SEL1 LC3D4S 2 0 LC3D3S 2 0 xxx xxx uuu uuu F24h CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC...

Страница 31: ...xxxx xxxx uuuu uuuu FEAh FSR1L_ SHAD Indirect Data Memory Address 1 Low Pointer Shadow xxxx xxxx uuuu uuuu FEBh FSR1H_ SHAD Indirect Data Memory Address 1 High Pointer Shadow xxxx xxxx uuuu uuuu FECh...

Страница 32: ...CALL allows programs to maintain tables of functions and provide another way to execute state machines or look up tables When performing a table read using a computed function CALL care should be exer...

Страница 33: ...then read write to TOSH TOSL STKPTR is 5 bits to allow detection of overflow and underflow During normal program operation CALL CALLW and Interrupts will increment STKPTR while RETLW RETURN and RETFIE...

Страница 34: ...ented to the empty state 0x1F 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x04 0x05 0x03 0x02 0x01 0x00 TOSH TOSL Rev 10 000043B 7 30 2013 STKPTR 0x06 After seven CALLs or six CALLs and an inter...

Страница 35: ...cted The FSRn register value is created by the pair FSRnH and FSRnL The FSR registers form a 16 bit address that allows an addressing space with 65536 locations These locations are divided into three...

Страница 36: ...FF 0x0000 0x7FFF 0xFFFF 0x0000 0x0FFF 0x1000 0x1FFF 0x2000 0x29AF 0x29B0 0x7FFF 0x8000 Reserved Reserved Traditional Data Memory Linear Data Memory Program Flash Memory FSR Address Range Note Not all...

Страница 37: ...ddress 0xFFF The addresses correspond to the absolute addresses of all SFR GPR and common registers FIGURE 3 9 TRADITIONAL DATA MEMORY MAP Direct Addressing 4 0 BSR 6 0 From Opcode 0 0 7 FSRxH 0 0 0 0...

Страница 38: ...constant data access easier the entire program Flash memory is mapped to the upper half of the FSR address space When the MSb of FSRnH is set the lower 15 bits are the address in program memory which...

Страница 39: ...Words There are several Configuration Word bits that allow different oscillator and memory protection options These are implemented as Configuration Word 1 at 8007h and Configuration Word 2 at 8008h...

Страница 40: ...TEN Clock Out Enable bit 1 CLKOUT function is disabled I O function on the CLKOUT pin 0 CLKOUT function is enabled on the CLKOUT pin bit 10 9 BOREN 1 0 Brown Out Reset Enable bits 2 11 BOR enabled 10...

Страница 41: ...onnected to CLKIN pin 010 HS oscillator High speed crystal resonator connected between OSC1 and OSC2 pins 001 XT oscillator Crystal resonator connected between OSC1 and OSC2 pins 000 LP oscillator Low...

Страница 42: ...selected 0 Brown out Reset voltage VBOR high trip point selected bit 9 STVREN Stack Overflow Underflow Reset Enable bit 1 Stack Overflow or Underflow will cause a Reset 0 Stack Overflow or Underflow...

Страница 43: ...setting See Section 4 4 Write Protection for more information 4 4 Write Protection Write protection allows the device to be protected from unintended self writes Applications such as bootloader softwa...

Страница 44: ...such as device programmers and debuggers may be used to read the Device ID and Revision ID 4 7 Register Definitions Device ID REGISTER 4 3 DEVID DEVICE ID REGISTER R R R R R R DEV 8 3 bit 13 bit 8 R...

Страница 45: ...ator allows internal circuits to power up and stabilize before switching to the 16 MHz HFINTOSC The oscillator module can be configured in one of the following clock modes 1 ECL External Clock Low Pow...

Страница 46: ...or 31 kHz Oscillator Prescaler HFINTOSC 1 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62 5 kHz 31 25 kHz 31 kHz IRCF 3 0 4 INTOSC Secondary Clock 1 Primary Clock HFINTOSC LFINTOSC to CPU an...

Страница 47: ...ck source is connected to the OSC1 input OSC2 CLKOUT is available for general purpose I O or CLKOUT Figure 5 2 shows the pin connections for EC mode EC mode has three power modes to select from throug...

Страница 48: ...crystal characteristics vary according to type package and manufacturer The user should consult the manufacturer data sheets for specifications and recommended application 2 Always verify oscillator...

Страница 49: ...e operating temperature Other factors affecting the oscillator frequency are threshold voltage variation component tolerances packaging variations in capacitance The user also needs to take into accou...

Страница 50: ...ter for the desired HF frequency and FOSC 2 0 100 or Set the System Clock Source SCS bits of the OSCCON register to 1x A fast start up oscillator allows internal circuits to power up and stabilize bef...

Страница 51: ...eady be shut down to save power see Figure 5 7 If this is the case there is a delay after the IRCF 3 0 bits of the OSCCON register are modified before the frequency selection takes place The OSCSTAT r...

Страница 52: ...TOSC LFINTOSC FSCM and WDT disabled HFINTOSC LFINTOSC Either FSCM or WDT enabled LFINTOSC HFINTOSC IRCF 3 0 System Clock 0 0 2 cycle Sync Running LFINTOSC HFINTOSC LFINTOSC turns off unless WDT or FSC...

Страница 53: ...Clock Monitor and or Two Speed Start up are enabled FCMEN 1 and or IESO 1 the device will operate using the internal oscillator INTOSC selected by the IRCF 3 0 bits whenever OSTS 0 When the OST period...

Страница 54: ...ions that make heavy use of the Sleep mode Two Speed Start up will remove the external oscillator start up time from the time spent awake and can reduce the overall power con sumption of the device Th...

Страница 55: ...clock cycles 4 OST timed out wait for falling edge of the internal oscillator 5 OSTS is set 6 System clock held low until the next falling edge of new clock LP XT or HS mode 7 System clock is switche...

Страница 56: ...condition exists the user must take the following actions to clear the condition before returning to normal operation with the external source The next sections describe how to clear the Fail Safe con...

Страница 57: ...Change the SCS bits in the OSCCON register to select the secondary oscillator The clock module will immediately switch to the secondary oscillator and the fail safe condition will be cleared If the F...

Страница 58: ...Value at all other Resets 1 Bit is set 0 Bit is cleared bit 7 Unimplemented Read as 0 bit 6 3 IRCF 3 0 Internal Oscillator Frequency Select bits 1111 16 MHz 1110 8 MHz 1101 4 MHz 1100 2 MHz 1011 1 MH...

Страница 59: ...Read as 0 bit 5 OSTS Oscillator Start up Timer Status bit When the FOSC 2 0 bits select HS XT or LP oscillator 1 OST has counted 1024 clocks device is clocked by the FOSC 2 0 bit selection 0 OST is c...

Страница 60: ...R OSTS HFIOFR LFIOFR HFIOFS 60 PIE2 OSFIE C2IE C1IE BCL1IE NCO1IE 77 PIR2 OSFIF C2IF C1IF BCL1IF NCO1IF 80 T1CON TMR1CS 1 0 T1CKPS 1 0 T1OSCEN T1SYNC TMR1ON 163 Legend unimplemented location read as 0...

Страница 61: ...n optional power up timer can be enabled to extend the Reset time after a BOR or POR event A simplified block diagram of the On chip Reset Circuit is shown in Figure 6 1 FIGURE 6 1 SIMPLIFIED BLOCK DI...

Страница 62: ...ents If VDD falls below Vpor for a duration greater than parameter TBORDC the device will reset See Figure 6 2 for more information TABLE 6 1 BOR OPERATING MODES 6 2 1 BOR IS ALWAYS ON When the BOREN...

Страница 63: ...If BOREN 1 0 in Configuration Words 01 SBOREN is read write but has no effect on the BOR bit 6 BORFS Brown Out Reset Fast Start bit 1 If BOREN 1 0 10 Disabled in Sleep or BOREN 1 0 01 Under software...

Страница 64: ...nstruction within the time out period The TO and PD bits in the STATUS register are changed to indicate the WDT Reset See Section 9 0 Watchdog Timer WDT for more information 6 7 RESET Instruction A RE...

Страница 65: ...ternal Oscillators PWRTEN 1 IESO 0 code execution 1 External Oscillators PWRTEN 0 IESO 0 Ext Oscillator Osc Start Up Timer code execution 1 TOST TPWRT TOST VDD Internal POR Internal RESET MCLR FOSC Be...

Страница 66: ...u u u 0 u u u 1 0 MCLR Reset during Sleep u u u u 0 u u u u RESET Instruction Executed 1 u u u u u u u u Stack Overflow Reset STVREN 1 u 1 u u u u u u u Stack Underflow Reset STVREN 1 Condition Progra...

Страница 67: ...s on condition bit 7 STKOVF Stack Overflow Flag bit 1 A Stack Overflow occurred 0 A Stack Overflow has not occurred or cleared by firmware bit 6 STKUNF Stack Underflow Flag bit 1 A Stack Underflow occ...

Страница 68: ...DY 64 PCON STKOVF STKUNF RWDT RMCLR RI POR BOR 68 STATUS TO PD Z DC C 19 WDTCON WDTPS 4 0 SWDTEN 88 Legend unimplemented bit reads as 0 Shaded cells are not used by Resets Name Bits Bit 7 Bit 6 Bit 13...

Страница 69: ...ode This chapter contains the following information for Interrupts Operation Interrupt Latency Interrupts During Sleep INT Pin Automatic Context Saving Many peripherals produce interrupts Refer to the...

Страница 70: ...e interrupt by polling the interrupt flag bits The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts Because the GIE bit is cleared any interrupt that occurs whil...

Страница 71: ...n at PC PC Inst 0004h NOP 2 Cycle Instruction at PC FSR ADDR PC 1 PC 2 0004h 0005h PC Inst 0004h NOP GIE PC PC 1 3 Cycle Instruction at PC Execute Interrupt Inst PC Interrupt Sampled during Q1 Inst PC...

Страница 72: ...0005h Inst 0004h Inst 0005h Forced NOP Inst PC Inst PC 1 Inst PC 1 Inst 0004h Forced NOP Inst PC Note 1 INTF flag is sampled here every Q1 2 Asynchronous interrupt latency 3 5 TCY Synchronous latency...

Страница 73: ...the interrupt will occur When the INTEDG bit is set the rising edge will cause the interrupt When the INTEDG bit is clear the falling edge will cause the interrupt The INTF bit of the INTCON register...

Страница 74: ...errupt 0 Disables the INT external interrupt bit 3 IOCIE Interrupt on Change Enable bit 1 Enables the interrupt on change 0 Disables the interrupt on change bit 2 TMR0IF Timer0 Overflow Interrupt Flag...

Страница 75: ...Enable bit 1 Enables the ADC interrupt 0 Disables the ADC interrupt bit 5 RCIE USART Receive Interrupt Enable bit 1 Enables the USART receive interrupt 0 Disables the USART receive interrupt bit 4 TXI...

Страница 76: ...Disables the Oscillator Fail interrupt bit 6 C2IE Comparator C2 Interrupt Enable bit 1 Enables the Comparator C2 interrupt 0 Disables the Comparator C2 interrupt bit 5 C1IE Comparator C1 Interrupt En...

Страница 77: ...t 7 4 Unimplemented Read as 0 bit 3 CLC4IE Configurable Logic Block 4 Interrupt Enable bit 1 Enables the CLC 4 interrupt 0 Disables the CLC 4 interrupt bit 2 CLC3IE Configurable Logic Block 3 Interrup...

Страница 78: ...5 RCIF USART Receive Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending bit 4 TXIF USART Transmit Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending bit 3 SSP1IF Sy...

Страница 79: ...C2 Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending bit 5 C1IF Comparator C1 Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending bit 4 Unimplemented Read as 0 bit...

Страница 80: ...nterrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending bit 2 CLC3IF Configurable Logic Block 3 Interrupt Flag bit 1 Interrupt is pending 0 Interrupt is not pending bit 1 CLC2IF Configurab...

Страница 81: ...IE INTE IOCIE TMR0IF INTF IOCIF 75 OPTION_REG WPUEN INTEDG TMR0CS TMR0SE PSA PS 2 0 154 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE TMR2IE TMR1IE 76 PIE2 OSFIE C2IE C1IE BCL1IE NCO1IE 77 PIE3 CLC4IE CLC3IE CLC...

Страница 82: ...ning during Sleep see individual peripheral for more information The first three events will cause a device Reset The last three events are considered a continuation of pro gram execution To determine...

Страница 83: ...ode is intended for use with these peripherals Brown out Reset BOR Watchdog Timer WDT External interrupt pin Interrupt on change pins Timer1 with external clock source The Complementary Waveform Gener...

Страница 84: ...current in Sleep faster wake up bit 0 Reserved Read as 1 Maintain this bit set Note 1 PIC16F1508 9 only 2 See Section 29 0 Electrical Specifications Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit...

Страница 85: ...from unexpected events The WDT has the following features Independent clock source Multiple operating modes WDT is always on WDT is off when in Sleep WDT is controlled by software WDT is always off C...

Страница 86: ...9 4 Clearing the WDT The WDT is cleared when any of the following condi tions occur Any Reset CLRWDT instruction is executed Device enters Sleep Device wakes up from Sleep Oscillator fail WDT is disab...

Страница 87: ...2 Interval 128s nominal 10000 1 2097152 221 Interval 64s nominal 01111 1 1048576 220 Interval 32s nominal 01110 1 524288 219 Interval 16s nominal 01101 1 262144 218 Interval 8s nominal 01100 1 131072...

Страница 88: ...3 0 SCS 1 0 59 PCON STKOVF STKUNF RWDT RMCLR RI POR BOR 68 STATUS TO PD Z DC C 19 WDTCON WDTPS 4 0 SWDTEN 88 Legend x unknown u unchanged unimplemented locations read as 0 Shaded cells are not used b...

Страница 89: ...red by hardware at completion of the read or write operation The inability to clear the WR bit in software prevents the accidental premature termination of a write operation The WREN bit when set will...

Страница 90: ...he very next cycle in the PMDATH PMDATL register pair therefore it can be read as two bytes in the following instructions PMDATH PMDATL register pair will hold this value until another read or until i...

Страница 91: ...STR PC 3 INSTR PC 4 instruction ignored Forced NOP INSTR PC 2 executed here instruction ignored Forced NOP This code block will read 1 word of program memory at the memory address PROG_ADDR_HI PROG_AD...

Страница 92: ...processor will always force two NOP instructions When an Erase Row or Program Row operation is being performed the processor will stall internal operations typical 2 ms until the operation is complete...

Страница 93: ...on The user must place two NOP instructions immediately following the WR bit set instruction The processor will halt internal operations for the typical 2 ms erase time This is not Sleep mode as the c...

Страница 94: ...s boundary MOVWF PMADRL MOVF ADDRH W Load upper 6 bits of erase address boundary MOVWF PMADRH BCF PMCON1 CFGS Not configuration space BSF PMCON1 FREE Specify an erase operation BSF PMCON1 WREN Enable...

Страница 95: ...he latches into Flash program memory 1 Set the WREN bit of the PMCON1 register 2 Clear the CFGS bit of the PMCON1 register 3 Set the LWLO bit of the PMCON1 register When the LWLO bit of the PMCON1 reg...

Страница 96: ...h 30 1Eh Write Latch 1 01h Write Latch 0 00h Addr Addr Addr 000h 001Fh 001Eh 0000h 0001h 001h 003Fh 003Eh 0020h 0021h 002h 005Fh 005Eh 0040h 0041h 3FEh 7FDFh 7FDEh 7FC0h 7FC1h 3FFh 7FFFh 7FFEh 7FE0h 7...

Страница 97: ...exceed the number of words per row word_cnt Last word to write Disable Interrupts GIE 0 Select Program or Config Memory CFGS Select Row Address PMADRH PMADRL Select Write Operation FREE 0 Load Write...

Страница 98: ...lower MOVWF PMDATL MOVIW FSR0 Load second data byte into upper MOVWF PMDATH MOVF PMADRL W Check if lower bits of address are 00000 XORLW 0x1F Check if we re on the last of 32 addresses ANDLW 0x1F BTF...

Страница 99: ...mage to contain the new data to be written into program memory 4 Load the starting address of the row to be rewritten 5 Erase the program memory row 6 Load the write latches with data from the RAM ima...

Страница 100: ...CFGS 1 EXAMPLE 10 4 CONFIGURATION WORD AND DEVICE ID ACCESS Address Function Read Access Write Access 8000h 8003h User IDs Yes Yes 8006h Device ID Revision ID Yes No 8007h 8008h Configuration Words 1...

Страница 101: ...s are compared with the intended data stored in RAM after the last write is complete FIGURE 10 8 FLASH PROGRAM MEMORY VERIFY FLOWCHART Start Verify Operation This routine assumes that the last row of...

Страница 102: ...1 Bit is set 0 Bit is cleared bit 7 6 Unimplemented Read as 0 bit 5 0 PMDAT 13 8 Read write value for Most Significant bits of program memory REGISTER 10 3 PMADRL PROGRAM MEMORY ADDRESS LOW BYTE REGIS...

Страница 103: ...on the next WR command hardware cleared upon completion 0 Performs a write operation on the next WR command bit 3 WRERR Program Erase Error Flag bit 1 Condition indicates an improper program or erase...

Страница 104: ...the PMCON1 register The value written to this register is used to unlock the writes There are specific timing requirements on these writes Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register...

Страница 105: ...ct as a write to the corresponding PORTx register A read of the LATx register reads of the values held in the I O PORT latches while a read of the PORTx register reads the actual I O pin value Ports t...

Страница 106: ...itions Alternate Pin Function Control REGISTER 11 1 APFCON ALTERNATE PIN FUNCTION CONTROL REGISTER U 0 U 0 U 0 R W 0 0 R W 0 0 U 0 R W 0 0 R W 0 0 SSSEL T1GSEL CLC1SEL NCO1SEL bit 7 bit 0 Legend R Rea...

Страница 107: ...analog functions on the pin to operate correctly The state of the ANSELA bits has no effect on digital output functions A pin with TRIS clear and ANSEL set will still operate as a digital output but...

Страница 108: ...corresponding LATA register Reads from PORTA register is return of actual I O pin values REGISTER 11 3 TRISA PORTA TRI STATE REGISTER U 0 U 0 R W 1 1 R W 1 1 U 1 R W 1 1 R W 1 1 R W 1 1 TRISA5 TRISA4...

Страница 109: ...U 0 R W 1 1 U 0 R W 1 1 R W 1 1 R W 1 1 ANSA4 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 u Bit is unchanged x Bit is unknown n n Value at POR and...

Страница 110: ...nabled 2 The weak pull up device is automatically disabled if the pin is configured as an output 3 For the WPUA3 bit when MCLRE 1 weak pull up is internally enabled but not reported here Name Bit 7 Bi...

Страница 111: ...Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly The state of the ANSELB bits has no effect o...

Страница 112: ...Port pin is VIL bit 3 0 Unimplemented Read as 0 Note 1 Writes to PORTB are actually written to corresponding LATB register Reads from PORTB register is return of actual I O pin values REGISTER 11 8 TR...

Страница 113: ...ctual I O pin values REGISTER 11 10 ANSELB PORTB ANALOG SELECT REGISTER U 0 U 0 R W 1 1 R W 1 1 U 0 U 0 U 0 U 0 ANSB5 ANSB4 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as...

Страница 114: ...REG register must be cleared for individual pull ups to be enabled 2 The weak pull up device is automatically disabled if the pin is configured as an output Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi...

Страница 115: ...LC bit high will cause all digital reads on the pin to be read as 0 and allow analog functions on the pin to operate correctly The state of the ANSELC bits has no effect on digital out put functions A...

Страница 116: ...SC1 TRISC0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 u Bit is unchanged x Bit is unknown n n Value at POR and BOR Value at all other Resets 1 Bit is set 0 Bit is c...

Страница 117: ...s assigned to port or digital special function bit 5 4 Unimplemented Read as 0 bit 3 0 ANSC 3 0 Analog Select between Analog or Digital Function on pins RC 3 0 respectively 1 Analog input Pin is assig...

Страница 118: ...falling edges simultaneously by setting both associated bits of the IOCxP and IOCxN registers respectively 12 3 Interrupt Flags The IOCAFx and IOCBFx bits located in the IOCAF and IOCBF registers resp...

Страница 119: ...GE BLOCK DIAGRAM PORTA EXAMPLE IOCANx IOCAPx Q2 Q4Q1 data bus 0 or 1 write IOCAFx IOCIE to data bus IOCAFx edge detect IOC interrupt to CPU core from all other IOCnFx individual pin detectors D Q S D...

Страница 120: ...le bit W Writable bit U Unimplemented bit read as 0 u Bit is unchanged x Bit is unknown n n Value at POR and BOR Value at all other Resets 1 Bit is set 0 Bit is cleared bit 7 6 Unimplemented Read as 0...

Страница 121: ...d bit read as 0 u Bit is unchanged x Bit is unknown n n Value at POR and BOR Value at all other Resets 1 Bit is set 0 Bit is cleared bit 7 4 IOCBN 7 4 Interrupt on Change PORTB Negative Edge Enable bi...

Страница 122: ...NTF IOCIF 75 IOCAF IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 121 IOCAN IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 121 IOCAP IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 121 IOCBF IOCBF7 IOCBF6 IOCBF5 IOCB...

Страница 123: ...reference supplied to the comparator modules Reference Section 17 0 Comparator Module for additional information To minimize current consumption when the FVR is disabled the FVR buffers should be tur...

Страница 124: ...ator Range Selection bit 3 1 VOUT VDD 4VT High Range 0 VOUT VDD 2VT Low Range bit 3 2 CDAFVR 1 0 Comparator FVR Buffer Gain Selection bits 1 11 Comparator FVR Buffer Gain is 4x with output voltage 4x...

Страница 125: ...ates in either high or low range The high range selected by setting the TSRNG bit of the FVRCON register provides a wider output voltage This provides more resolution over the temperature range but ma...

Страница 126: ...9 TABLE 14 2 SUMMARY OF REGISTERS ASSOCIATED WITH THE TEMPERATURE INDICATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR 1 0 ADFVR 1 0 1...

Страница 127: ...s the block diagram of the ADC The ADC voltage reference is software selectable to be either internally generated or externally supplied The ADC can generate an interrupt upon completion of a conversi...

Страница 128: ...uses a positive and a negative voltage reference The positive reference is labeled ref and the negative reference is labeled ref The positive voltage reference ref is selected by the ADPREF bits in t...

Страница 129: ...1 0 6 0 s 1 0 6 0 s 1 0 6 0 s Legend Shaded cells are outside of recommended range Note The TAD period when using the FRC clock source can fall within a specified range see TAD parameter The TAD perio...

Страница 130: ...line code execu tion the GIE and PEIE bits of the INTCON register must be disabled If the GIE and PEIE bits of the INTCON register are enabled execution will switch to the Interrupt Service Routine 15...

Страница 131: ...he ADC interrupt is disabled the ADC module is turned off after the conversion com pletes although the ADON bit remains set When the ADC clock source is something other than FRC a SLEEP instruction ca...

Страница 132: ...ting for the ADC interrupt interrupts enabled 7 Read ADC Result 8 Clear the ADC interrupt flag required if interrupt is enabled EXAMPLE 15 1 ADC CONVERSION Note 1 The global interrupt can be disabled...

Страница 133: ...001 AN9 01010 AN10 01011 AN11 01100 Reserved No channel connected 11100 Reserved No channel connected 11101 Temperature Indicator 1 11110 DAC Digital to Analog Converter 3 11111 FVR Fixed Voltage Refe...

Страница 134: ...lt is loaded 0 Left justified Six Least Significant bits of ADRESL are set to 0 when the conversion result is loaded bit 6 4 ADCS 2 0 ADC Conversion Clock Select bits 000 FOSC 2 001 FOSC 8 010 FOSC 32...

Страница 135: ...t 0 Bit is cleared bit 7 4 TRIGSEL 3 0 Auto Conversion Trigger Selection bits 1 0000 No auto conversion trigger selected 0001 Reserved 0010 Reserved 0011 Timer0 T0_overflow 2 0100 Timer1 T1_overflow 2...

Страница 136: ...esets 1 Bit is set 0 Bit is cleared bit 7 0 ADRES 9 2 ADC Result Register bits Upper eight bits of 10 bit conversion result REGISTER 15 5 ADRESL ADC RESULT REGISTER LOW ADRESL ADFM 0 R W x u R W x u R...

Страница 137: ...esets 1 Bit is set 0 Bit is cleared bit 7 2 Reserved Do not use bit 1 0 ADRES 9 8 ADC Result Register bits Upper two bits of 10 bit conversion result REGISTER 15 7 ADRESL ADC RESULT REGISTER LOW ADRES...

Страница 138: ...LSb error is used 1 024 steps for the ADC The 1 2 LSb error is the maximum error allowed for the ADC to meet its specified resolution EQUATION 15 1 ACQUISITION TIME EXAMPLE TACQ Amplifier Settling Ti...

Страница 139: ...nt at the pin due to varies injunctions RIC Interconnect Resistance RSS Resistance of Sampling switch SS Sampling Switch VT Threshold Voltage VA RS RSS SS Sampling switch CHOLD 10 pF Ref 5 6 7 8 91011...

Страница 140: ...110 ANSELB ANSB5 ANSB4 114 ANSELC ANSC7 ANSC6 ANSC3 ANSC2 ANSC1 ANSC0 118 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 75 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE TMR2IE TMR1IE 76 PIR1 TMR1GIF ADIF...

Страница 141: ...f the DAC can be connected to Vss The output of the DAC DACx_output can be selected as a reference voltage to the following Comparator positive input ADC input channel DACxOUT1 pin DACxOUT2 pin The Di...

Страница 142: ...g the respective DACOEn bit s of the DACxCON0 register Selecting the DAC reference voltage for output on either DACxOUTn pin automatically overrides the digital output buffer the weak pull up and digi...

Страница 143: ...nnected from the DACxOUT1 pin bit 4 DACOE2 DAC Voltage Output Enable bit 1 DACx voltage level is output on the DACxOUT2 pin 0 DACx voltage level is disconnected from the DACxOUT2 pin bit 3 Unimplement...

Страница 144: ...le comparator is shown in Figure 17 2 along with the relationship between the analog input levels and the digital output When the analog voltage at VIN is less than the analog voltage at VIN the outpu...

Страница 145: ...bled 17 2 3 COMPARATOR NEGATIVE INPUT SELECTION The CxNCH 2 0 bits of the CMxCON0 register direct one of the input sources to the comparator inverting input 17 2 4 COMPARATOR OUTPUT SELECTION The outp...

Страница 146: ...erefore must be between VSS and VDD If the input voltage deviates from this range by more than 0 6V in either direction one of the diodes is for ward biased and a latch up may occur A maximum source i...

Страница 147: ...n interrupt can be generated upon a change in the output value of the comparator for each comparator a rising edge detector and a falling edge detector are present When either edge detector is trigger...

Страница 148: ...rted polarity 1 CxVP CxVN 0 CxVP CxVN bit 5 CxOE Comparator Output Enable bit 1 CxOUT is present on the CxOUT pin Requires that the associated TRIS bit be cleared to actually drive the pin Not affecte...

Страница 149: ...xOUT bit 0 No interrupt flag will be set on a negative going edge of the CxOUT bit bit 5 4 CxPCH 1 0 Comparator Positive Input Channel Select bits 11 CxVP connects to VSS 10 CxVP connects to FVR Volta...

Страница 150: ...150 CMOUT MC2OUT MC1OUT 150 DAC1CON0 DACEN DACOE1 DACOE2 DACPSS 144 DAC1CON1 DACR 4 0 144 FVRCON FVREN FVRRDY TSEN TSRNG CDAFVR 1 0 ADFVR 1 0 125 INTCON GIE PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF 75...

Страница 151: ...e OPTION_REG register When TMR0 is written the increment is inhibited for two instruction cycles immediately following the write 18 1 2 8 BIT COUNTER MODE In 8 Bit Counter mode the Timer0 module will...

Страница 152: ...lag bit of the INTCON register is set every time the TMR0 register overflows regardless of whether or not the Timer0 interrupt is enabled The TMR0IF bit can only be cleared in software The Timer0 inte...

Страница 153: ...pin bit 5 TMR0CS Timer0 Clock Source Select bit 1 Transition on T0CKI pin 0 Internal instruction cycle clock FOSC 4 bit 4 TMR0SE Timer0 Source Edge Select bit 1 Increment on high to low transition on...

Страница 154: ...9 1 is a block diagram of the Timer1 module FIGURE 19 1 TIMER1 BLOCK DIAGRAM 00 11 10 01 T1G T0_overflow C1OUT_sync C2OUT_sync T1GSS 1 0 T1GPOL 0 1 Single Pulse Acq Control 1 0 T1GSPM D Q TMR1ON T1GTM...

Страница 155: ...ck cycle Due to this condition a 2 LSB error in resolution will occur when reading the Timer1 value To utilize the full resolution of Timer1 an asynchronous input signal must be used to gate the Timer...

Страница 156: ...roduce an unpredictable value in the TMR1H TMR1L register pair 19 6 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry This is al...

Страница 157: ...r1 will be fully enabled on the next incrementing edge On the next trailing edge of the pulse the T1GGO DONE bit will automatically be cleared No other gate events will be allowed to increment Timer1...

Страница 158: ...r must be set T1SYNC bit of the T1CON register must be set TMR1CS bits of the T1CON register must be configured T1OSCEN bit of the T1CON register must be configured The device will wake up on an overf...

Страница 159: ...2015 Microchip Technology Inc FIGURE 19 3 TIMER1 GATE ENABLE MODE FIGURE 19 4 TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N N 1 N 2 N 3 N 4 TMR1GE T1GPOL T1GTM t1g_in T1CKI T1GVAL...

Страница 160: ...MER1 GATE SINGLE PULSE MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N N 1 N 2 T1GSPM T1GGO DONE Set by software Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL...

Страница 161: ...ULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL t1g_in T1CKI T1GVAL Timer1 N N 1 N 2 T1GSPM T1GGO DONE Set by software Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GV...

Страница 162: ...or If T1OSCEN 0 External clock from T1CKI pin on the rising edge If T1OSCEN 1 Crystal oscillator on SOSCI SOSCO pins 01 Timer1 clock source is system clock FOSC 00 Timer1 clock source is instruction c...

Страница 163: ...1 counts when gate is low bit 5 T1GTM Timer1 Gate Toggle Mode bit 1 Timer1 Gate Toggle mode is enabled 0 Timer1 Gate Toggle mode is disabled and toggle flip flop is cleared Timer1 gate flip flop toggl...

Страница 164: ...GIE ADIE RCIE TXIE SSP1IE TMR2IE TMR1IE 76 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF TMR2IF TMR1IF 79 TMR1H Holding Register for the Most Significant Byte of the 16 bit TMR1 Count 159 TMR1L Holding Register...

Страница 165: ...aler 1 1 to 1 16 Interrupt on TMR2 match with PR2 See Figure 20 1 for a block diagram of Timer2 FIGURE 20 1 TIMER2 BLOCK DIAGRAM FIGURE 20 2 TIMER2 TIMING DIAGRAM Prescaler 1 1 1 4 1 16 1 64 Fosc 4 2...

Страница 166: ...ice interrupt The Timer2 output signal T2_match provides the input for the 4 bit counter postscaler This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register...

Страница 167: ...01 1 6 Postscaler 0110 1 7 Postscaler 0111 1 8 Postscaler 1000 1 9 Postscaler 1001 1 10 Postscaler 1010 1 11 Postscaler 1011 1 12 Postscaler 1100 1 13 Postscaler 1101 1 14 Postscaler 1110 1 15 Postsca...

Страница 168: ...n one of two modes Serial Peripheral Interface SPI Inter Integrated Circuit I2C The SPI interface supports the following modes and features Master mode Slave mode Clock Parity Slave Select Synchroniza...

Страница 169: ...control different operational aspects of the same module while SSPxCON1 and SSP2CON1 control the same features for two different modules 2 Throughout this section generic refer ences to an MSSPx modul...

Страница 170: ...L F1508 9 FIGURE 21 3 MSSP BLOCK DIAGRAM I2 C SLAVE MODE Read Write SSPxBUF 8 8 SSPxSR 8 SCLx SDAx Internal data bus MSb LSb SSPxMSK 8 8 8 Match detect SSPxADD Start and Stop bit Detect Addr Match Set...

Страница 171: ...Ox output pin which is connected to and received by the slave s SDIx input pin The slave device trans mits information out on its SDOx output pin which is connected to and received by the master s SDI...

Страница 172: ...e In SPI master mode SSPxADD can be loaded with a value used in the Baud Rate Generator More informa tion on the Baud Rate Generator is available in Section21 7 Baud Rate Generator SSPxSR is the shift...

Страница 173: ...ift register SSPxSR and a buffer register SSPxBUF The SSPxSR shifts the data in and out of the device MSb first The SSPxBUF holds the data that was written to the SSPxSR until the received data is rea...

Страница 174: ...ECTION SPI Master SSPM 3 0 00xx 1010 SDOx SDOx SDIx SDIx Serial Input Buffer SSPxBUF Serial Input Buffer SSPxBUF Shift Register SSPxSR Shift Register SSPxSR SPI Slave SSPM 3 0 010x MSb MSb LSb LSb SCK...

Страница 175: ...register and the CKE bit of the SSPxSTAT register This then would give waveforms for SPI communication as shown in Figure 21 6 Figure 21 8 Figure 21 9 and Figure 21 10 where the MSb is transmitted fi...

Страница 176: ...3 register will enable writes to the SSPxBUF register even if the previous byte has not been read This allows the software to ignore data that may not apply to it 21 2 5 SLAVE SELECT SYNCHRONIZATION T...

Страница 177: ...SCK SDOx SDOx SDOx SDOx SDIx SDIx SDIx SDIx General I O SPI Master SPI Slave 1 SPI Slave 2 SPI Slave 3 SSx SSx SSx Rev 10 000082A 7 30 2013 SCKx CKP 1 SCKx CKP 0 Input Sample SDIx bit 7 SDOx bit 7 bit...

Страница 178: ...bit 7 SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SSPxIF Interrupt CKE 0 CKE 0 Write to SSPxBUF SSPxSR to SSPxBUF SSx Flag Optional bit 0 detection active Write Collision Valid SCKx CKP 1 SC...

Страница 179: ...ister operates asynchronously to the device This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit Receive Shift register When all eight bits have been received...

Страница 180: ...ion of the SDAx line while the SCLx line is held high Address and data bytes are sent out Most Significant bit MSb first The Read Write bit is sent out as a logical one when the master intends to read...

Страница 181: ...time When this occurs the process of arbitration begins Each transmitter checks the level of the SDAx data line and compares it to the level that it expects to find The first transmitter to observe th...

Страница 182: ...pin is selected by the SDAHT bit of the SSPxCON3 register Hold time is the time SDAx is held valid after the falling edge of SCLx Setting the SDAHT bit selects a longer 300 ns mini mum hold time and...

Страница 183: ...ave Figure 21 13 shows the wave form for a Restart condition In 10 bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave Once a slave has been fully a...

Страница 184: ...ee Section21 5 9 SSPx Mask Register for more information 21 5 1 1 I2C Slave 7 bit Addressing Mode In 7 bit Addressing mode the LSb of the received data byte is ignored when determining if there is an...

Страница 185: ...the steps that need to be taken by slave software to use these options for I2 C communi cation Figure 21 16 displays a module using both address and data holding Figure 21 17 includes the operation w...

Страница 186: ...1 A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDAx SCLx SSPxIF BF SSPOV 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 9 9 ACK is not sent SSPOV set because SSPxBUF is stil...

Страница 187: ...P SSPxIF set on 9th SCLx is not held CKP is written to 1 in software CKP is written to 1 in software ACK low because falling edge of SCLx releasing SCLx ACK is not sent Bus Master sends CKP SSPOV BF...

Страница 188: ...on 9th falling edge of SCLx after ACK CKP set by software SCLx is released Slave software 9 ACKTIM cleared by hardware in 9th rising edge of SCLx sets ACKDT to not ACK When DHEN 1 CKP is cleared by h...

Страница 189: ...t by software read any time before next byte is loaded release SCLx on 9th rising edge of SCLx Received address is loaded into SSPxBUF Slave software clears ACKDT to ACK R W 0 Master releases SDAx to...

Страница 190: ...edge of the ninth clock pulse 21 5 3 1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDAx line If a bus collision is detected and the SBCDE bit of the SS...

Страница 191: ...8 9 1 2 3 4 5 6 7 8 9 SDAx SCLx SSPxIF BF CKP ACKSTAT R W D A S P Received address When R W is set R W is copied from the Indicates an address is read from SSPxBUF SCLx is always held low after 9th SC...

Страница 192: ...the interrupt 6 Slave reads the address value from the SSPxBUF register clearing the BF bit 7 Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit of the...

Страница 193: ...ss is read from SSPxBUF BF is automatically cleared after 8th falling edge of SCLx Data to transmit is loaded into SSPxBUF Cleared by software Slave clears ACKDT to ACK address Master s ACK response i...

Страница 194: ...ve loads high address into SSPxADD 13 Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCLx pulse SSPxIF is set 14 If SEN bit of SSPxCON2 is set CKP is cleared by hard...

Страница 195: ...D6 D5 D4 D3 D2 D1 D0 SDAx SCLx UA CKP 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Master sends Stop condition Cleared by software Receive address is Software updates SSPx...

Страница 196: ...9 S ACK ACK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 SSPxBUF is read from Received data SSPxBUF can be read anytime before the next received byte Cleared by software falling edge of SCLx not allowed u...

Страница 197: ...1 2 3 4 5 6 7 8 9 ACK 1 P Master sends Stop condition Master sends not ACK Master sends Restart event ACK R W 0 S Cleared by software After SSPxADD is updated UA is cleared and SCLx is released High...

Страница 198: ...red by hardware after the eighth falling edge of SCLx for a received matching address byte When the DHEN bit of SSPxCON3 is set CKP is cleared after the eighth falling edge of SCLx for received data S...

Страница 199: ...the AHEN bit of the SSPxCON3 register is set just as with any other address reception the slave hard ware will stretch the clock after the eighth falling edge of SCLx The slave must then set its ACKD...

Страница 200: ...serial transfer the I2C bus will not be released In Master Transmitter mode serial data is output through SDAx while SCLx outputs the serial clock The first byte transmitted contains the slave address...

Страница 201: ...low by an external device Figure 21 25 FIGURE 21 25 BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION 21 6 3 WCOL STATUS FLAG If the user writes the SSPxBUF when a Start Restart Stop Receive or Trans...

Страница 202: ...count When the Baud Rate Generator times out TBRG the SEN bit of the SSPxCON2 register will be automatically cleared by hardware the Baud Rate Generator is suspended leaving the SDAx line held low an...

Страница 203: ...one TBRG while SCLx is high SCLx is asserted low Following this the RSEN bit of the SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded leaving the SDAx p...

Страница 204: ...ock transmission of the address the SSPxIF is set the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPxBUF takes place holding SCLx low and allowing SDAx to...

Страница 205: ...dress to Slave 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared by software service routine SSPxBUF is written by software from SSP interrupt After Start condition SEN cleared by hardware S SSPxBUF writt...

Страница 206: ...er writes the SSPxBUF when a receive is already in progress i e SSPxSR is still shifting in a data byte the WCOL bit is set and the contents of the buffer are unchanged the write does not occur 21 6 7...

Страница 207: ...SCLx 1 while CPU SSPxSTAT 0 ACK Cleared by software Cleared by software Set SSPxIF interrupt at end of receive Set P bit SSPxSTAT 4 and SSPxIF Cleared in software ACK from Master Set SSPxIF at end Se...

Страница 208: ...cur 21 6 9 STOP CONDITION TIMING A Stop bit is asserted on the SDAx pin at the end of a receive transmit by setting the Stop Sequence Enable bit PEN bit of the SSPxCON2 register At the end of a receiv...

Страница 209: ...a 1 and the data sampled on the SDAx pin is 0 then a bus collision has taken place The master will set the Bus Collision Interrupt Flag BCLxIF and reset the I2C port to its Idle state Figure 21 32 If...

Страница 210: ...LLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE SDAx SCLx BCLxIF SDAx released SDAx line pulled low by another source Sample SDAx While SCLx is high data does not match what is driven Bus collision has oc...

Страница 211: ...d on the SDA pin the SDA pin is asserted low at the end of the BRG count The Baud Rate Generator is then reloaded and counts down to zero if the SCL pin is sampled as 0 during this time a bus collisio...

Страница 212: ...Set SEN enable Start sequence if SDAx 1 SCLx 1 TBRG TBRG SDAx 0 SCLx 1 BCLxIF S SSPxIF Interrupt cleared by software bus collision occurs Set BCLxIF SCLx 0 before BRG time out 0 0 0 0 SDAx SCLx SEN S...

Страница 213: ...times out no bus collision occurs because no two masters can assert SDAx at exactly the same time If SCLx goes from high to low before the BRG times out and SDAx has not already been asserted a bus c...

Страница 214: ...e Baud Rate Generator is loaded with SSPxADD and counts down to 0 After the BRG times out SDAx is sampled If SDAx is sampled low a bus collision has occurred This is due to another master attempting t...

Страница 215: ...F RCIF TXIF SSP1IF TMR2IF TMR1IF 79 PIR2 OSFIF C2IF C1IF BCL1IF NCO1IF 80 TRISA TRISA5 TRISA4 1 TRISA2 TRISA1 TRISA0 109 SSP1ADD ADD 7 0 222 SSP1BUF MSSP Receive Buffer Transmit Register 173 SSP1CON1...

Страница 216: ...he logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in Table 21 4 demonstrates clock rates based on instruction cycles and the BRG value loaded into SS...

Страница 217: ...es that the last byte received or transmitted was address bit 4 P Stop bit I2C mode only This bit is cleared when the MSSP module is disabled SSPEN is cleared 1 Indicates that a Stop bit has been dete...

Страница 218: ...SPI mode 1 Enables serial port and configures SCKx SDOx SDIx and SSx as the source of the serial port pins 2 0 Disables serial port and configures these pins as I O port pins In I2C mode 1 Enables th...

Страница 219: ...nable bit in I2 C Master mode only In Master Receive mode 1 Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit Automatically cleared by hardware 0 Acknowledge sequence idl...

Страница 220: ...nd ACK is generated for a received address data byte ignoring the state of the SSPOV bit only if the BF bit 0 0 SSPxBUF is only updated when SSPOV is clear bit 3 SDAHT SDAx Hold Time Selection bit I2...

Страница 221: ...PxADD MSSP ADDRESS AND BAUD RATE REGISTER I2C MODE R W 0 0 R W 0 0 R W 0 0 R W 0 0 R W 0 0 R W 0 0 R W 0 0 R W 0 0 ADD 7 0 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as...

Страница 222: ...module includes the following capabilities Full duplex asynchronous transmit and receive Two character input buffer One character output buffer Programmable 8 bit or 9 bit character length Address de...

Страница 223: ...ister 22 1 Register 22 2 and Register 22 3 respectively When the receiver or transmitter section is not enabled then the corresponding RX or TX pin may be used for general purpose input and output n M...

Страница 224: ...alog peripheral the analog I O function must be disabled by clearing the corresponding ANSEL bit 22 1 1 2 Transmitting Data A transmission is initiated by writing a character to the TXREG register If...

Страница 225: ...T Baud Rate Generator BRG 2 Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit 3 If 9 bit transmission is desired set the TX9 con trol bit A set ninth data bit will...

Страница 226: ...R0IF INTF IOCIF 75 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE TMR2IE TMR1IE 76 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF TMR2IF TMR1IF 79 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 234 SPBRGL BRG 7 0 236 SPBRGH B...

Страница 227: ...circuit aborts character reception without generating an error and resumes looking for the falling edge of the Start bit If the Start bit zero verification succeeds then the data recovery circuit coun...

Страница 228: ...he error must be cleared by either clearing the CREN bit of the RCSTA register or by resetting the EUSART by clearing the SPEN bit of the RCSTA register 22 1 2 6 Receiving 9 bit Characters The EUSART...

Страница 229: ...aud rate see Section22 4 EUSART Baud Rate Generator BRG 2 Clear the ANSEL bit for the RX pin if applicable 3 Enable the serial port by setting the SPEN bit The SYNC bit must be clear for asynchronous...

Страница 230: ...MR0IF INTF IOCIF 75 PIE1 TMR1GIE ADIE RCIE TXIE SSP1IE TMR2IE TMR1IE 76 PIR1 TMR1GIF ADIF RCIF TXIF SSP1IF TMR2IF TMR1IF 79 RCREG EUSART Receive Data Register 228 RCSTA SPEN RX9 SREN CREN ADDEN FERR O...

Страница 231: ...ver the INTOSC frequency may drift as VDD or temperature changes and this directly affects the asynchronous baud rate The Auto Baud Detect feature see Section22 4 1 Auto Baud Detect can be used to com...

Страница 232: ...from BRG 0 Slave mode clock from external source bit 6 TX9 9 bit Transmit Enable bit 1 Selects 9 bit transmission 0 Selects 8 bit transmission bit 5 TXEN Transmit Enable bit 1 1 Transmit enabled 0 Tra...

Страница 233: ...les single receive This bit is cleared after reception is complete Synchronous mode Slave Don t care bit 4 CREN Continuous Receive Enable bit Asynchronous mode 1 Enables receiver 0 Disables receiver S...

Страница 234: ...us mode Don t care bit 5 Unimplemented Read as 0 bit 4 SCKP Synchronous Clock Polarity Select bit Asynchronous mode 1 Transmit inverted data to the TX CK pin 0 Transmit non inverted data to the TX CK...

Страница 235: ...ave been computed for your convenience and are shown in Table 22 3 It may be advantageous to use the high baud rate BRGH 1 or the 16 bit BRG BRG16 1 to reduce the baud rate error The 16 bit BRG mode i...

Страница 236: ...hronous 0 1 1 16 bit Asynchronous FOSC 4 n 1 1 0 x 8 bit Synchronous 1 1 x 16 bit Synchronous Legend x Don t care n value of SPBRGH SPBRGL register pair Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1...

Страница 237: ...1 000 MHz Actual Rate Error SPBRG value decimal Actual Rate Error SPBRG value decimal Actual Rate Error SPBRG value decimal Actual Rate Error SPBRG value decimal 300 300 0 16 207 300 0 00 191 300 0 16...

Страница 238: ...0 0 00 2303 1200 1200 0 03 1041 1200 0 00 959 1200 5 0 04 832 1200 0 00 575 2400 2399 0 03 520 2400 0 00 479 2398 0 08 416 2400 0 00 287 9600 9615 0 16 129 9600 0 00 119 9615 0 16 103 9600 0 00 71 10...

Страница 239: ...0 143 57 6k 57 47k 0 22 86 57 60k 0 00 79 57 97k 0 64 68 57 60k 0 00 47 115 2k 116 3k 0 94 42 115 2k 0 00 39 114 29k 0 79 34 115 2k 0 00 23 BAUD RATE SYNC 0 BRGH 1 BRG16 1 or SYNC 1 BRG16 1 FOSC 8 000...

Страница 240: ...G auto baud clock is determined by the BRG16 and BRGH bits as shown in Table 22 6 During ABD both the SPBRGH and SPBRGL registers are used as a 16 bit counter independent of the BRG16 bit setting Whil...

Страница 241: ...The EUSART module generates an RCIF interrupt coincident with the wake up event The interrupt is generated synchronously to the Q clocks in normal CPU operating modes Figure 22 7 and asynchronously i...

Страница 242: ...due to User Read of RCREG Note 1 The EUSART remains in Idle while the WUE bit is set Q1Q2Q3 Q4 Q1Q2 Q3Q4 Q1Q2Q3Q4 Q1 Q2 Q3Q4 Q1Q2Q3 Q4 Q1Q2Q3Q4 Q1Q2Q3 Q4 Q1Q2 Q3Q4 OSC1 WUE bit RX DT Line RCIF Bit Se...

Страница 243: ...G with a dummy character to initiate transmission the value is ignored 4 Write 55h to TXREG to load the Sync character into the transmit FIFO buffer 5 After the Break has been sent the SENDB bit is re...

Страница 244: ...g edge of each clock One clock cycle is generated for each data bit Only as many clock cycles are gener ated as there are data bits 22 5 1 2 Clock Polarity A clock polarity option is provided for Micr...

Страница 245: ...9 SREN CREN ADDEN FERR OERR RX9D 234 SPBRGL BRG 7 0 236 SPBRGH BRG 15 8 236 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 113 TXREG EUSART Transmit Data Register 225 TXSTA CSRC TX9 TXE...

Страница 246: ...happens the OERR bit of the RCSTA register is set Previous data in the FIFO will not be overwritten The two characters in the FIFO buffer can be read however no additional characters will be received...

Страница 247: ...XIF SSP1IF TMR2IF TMR1IF 79 RCREG EUSART Receive Data Register 228 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 234 SPBRGL BRG 7 0 236 SPBRGH BRG 15 8 236 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRI...

Страница 248: ...bit will now be set 5 If the PEIE and TXIE bits are set the interrupt will wake the device from Sleep and execute the next instruction If the GIE bit is also set the program will call the Interrupt Se...

Страница 249: ...9 bit reception is desired set the RX9 bit 5 Set the CREN bit to enable reception 6 The RCIF bit will be set when reception is complete An interrupt will be generated if the RCIE bit was set 7 If 9 bi...

Страница 250: ...PWM operation For a step by step procedure on how to set up this module for PWM operation refer to Section 23 1 9 Setup for PWM Operation using PWMx Pins FIGURE 23 1 SIMPLIFIED PWM BLOCK DIAGRAM Rev 1...

Страница 251: ...s 23 1 4 PWM DUTY CYCLE The PWM duty cycle is specified by writing a 10 bit value to the PWMxDCH and PWMxDCL register pair The PWMxDCH register contains the eight MSbs and the PWMxDCL 7 6 the two LSbs...

Страница 252: ...EQUENCY The PWM frequency is derived from the system clock frequency FOSC Any changes in the system clock frequency will result in changes to the PWM frequency Refer to Section 5 0 Oscillator Module W...

Страница 253: ...the T2CKPS bits of the T2CON register with the Timer2 prescale value Enable Timer2 by setting the TMR2ON bit of the T2CON register 6 Enable PWM output pin and wait until Timer2 overflows TMR2IF bit o...

Страница 254: ...it read as 0 u Bit is unchanged x Bit is unknown n n Value at POR and BOR Value at all other Resets 1 Bit is set 0 Bit is cleared bit 7 PWMxEN PWM Module Enable bit 1 PWM module is enabled 0 PWM modul...

Страница 255: ...PWMxDCL 7 6 PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle The MSbs are found in the PWMxDCH register bit 5 0 Unimplemented Read as 0 TABLE 23 3 SUMMARY OF REGIST...

Страница 256: ...o an output pin Refer to Figure 24 1 for a simplified diagram showing signal flow through the CLCx Possible configurations include Combinatorial Logic AND NAND AND OR AND OR INVERT OR XOR OR XNOR Latc...

Страница 257: ...labeled lcxd1 through lcxd4 indicate the MUX output for the selected data input D1S through D4S are abbreviations for the MUX select input codes LCxD1S 2 0 through LCxD4S 2 0 respectively Selecting a...

Страница 258: ...its to zero and use the gate polarity bit to set the desired level Data gating is configured with the logic gate select registers as follows Gate 1 CLCxGLS0 Register 24 5 Gate 2 CLCxGLS1 Register 24 6...

Страница 259: ...e detector is triggered and its asso ciated enable bit is set The LCxINTP enables rising edge interrupts and the LCxINTN bit enables falling edge interrupts Both are located in the CLCxCON register To...

Страница 260: ...LCxD1G1N LCxD2G1T LCxD2G1N LCxD3G1T LCxD3G1N LCxD4G1T LCxD4G1N LCxD1S 4 0 LCxD2S 4 0 LCxD3S 4 0 LCxD4S 4 0 LCx_in 0 LCx_in 31 00000 11111 Data Selection Note All controls are undefined at power up lc...

Страница 261: ...1 lcxg2 lcxg3 lcxg4 lcxq S R Q lcxq lcxg1 lcxg2 lcxg3 lcxg4 lcxg1 lcxg2 lcxg3 lcxg4 lcxq 1 Input D Flip Flop with S and R 2 Input D Flip Flop with R J K Flip Flop with R 1 Input Transparent Latch with...

Страница 262: ...Output Enable bit 1 Configurable logic cell port pin output enabled 0 Configurable logic cell port pin output disabled bit 5 LCxOUT Configurable Logic Cell Data Output bit Read only logic cell output...

Страница 263: ...0 The output of the logic cell is not inverted bit 6 4 Unimplemented Read as 0 bit 3 LCxG4POL Gate 4 Output Polarity Control bit 1 The output of gate 4 is inverted when applied to the logic cell 0 Th...

Страница 264: ...LCx_in 11 is selected for lcxd2 110 LCx_in 10 is selected for lcxd2 101 LCx_in 9 is selected for lcxd2 100 LCx_in 8 is selected for lcxd2 011 LCx_in 7 is selected for lcxd2 010 LCx_in 6 is selected fo...

Страница 265: ...n 3 is selected for lcxd4 110 LCx_in 2 is selected for lcxd4 101 LCx_in 1 is selected for lcxd4 100 LCx_in 0 is selected for lcxd4 011 LCx_in 15 is selected for lcxd4 010 LCx_in 14 is selected for lcx...

Страница 266: ...xG1D4N Gate 1 Data 4 Negated inverted bit 1 lcxd4N is gated into lcxg1 0 lcxd4N is not gated into lcxg1 bit 5 LCxG1D3T Gate 1 Data 3 True non inverted bit 1 lcxd3T is gated into lcxg1 0 lcxd3T is not...

Страница 267: ...G2D4N Gate 2 Data 4 Negated inverted bit 1 lcxd4N is gated into lcxg2 0 lcxd4N is not gated into lcxg2 bit 5 LCxG2D3T Gate 2 Data 3 True non inverted bit 1 lcxd3T is gated into lcxg2 0 lcxd3T is not g...

Страница 268: ...xG3D4N Gate 3 Data 4 Negated inverted bit 1 lcxd4N is gated into lcxg3 0 lcxd4N is not gated into lcxg3 bit 5 LCxG3D3T Gate 3 Data 3 True non inverted bit 1 lcxd3T is gated into lcxg3 0 lcxd3T is not...

Страница 269: ...G4D4N Gate 4 Data 4 Negated inverted bit 1 lcxd4N is gated into lcxg4 0 lcxd4N is not gated into lcxg4 bit 5 LCxG4D3T Gate 4 Data 3 True non inverted bit 1 lcxd3T is gated into lcxg4 0 lcxd3T is not g...

Страница 270: ...bit 0 Legend R Readable bit W Writable bit U Unimplemented bit read as 0 u Bit is unchanged x Bit is unknown n n Value at POR and BOR Value at all other Resets 1 Bit is set 0 Bit is cleared bit 7 4 Un...

Страница 271: ...264 CLC2SEL0 LC2D2S 2 0 LC2D1S 2 0 265 CLC2SEL1 LC2D4S 2 0 LC2D3S 2 0 266 CLC3CON LC3EN LC3OE LC3OUT LC3INTP LC3INTN LC3MODE 2 0 263 CLC3GLS0 LC3G1D4T LC3G1D4N LC3G1D3T LC3G1D3N LC3G1D2T LC3G1D2N LC3G...

Страница 272: ...iod changes in discrete steps to create an average frequency This output depends on the ability of the receiving circuit i e CWG or external resonant converter circuitry to average the NCOx output to...

Страница 273: ...xOUT NCOx NCO_interrupt set bit NCOxIF EN Ripple Counter 3 NxPWS 2 0 R Fixed Duty Cycle Mode Circuitry Pulse Frequency Mode Circuitry 1 NCOx_clk Note 1 The increment registers are double buffered to a...

Страница 274: ...interrupt for the result ing output transition The NCOx output can be used internally by source code or other peripherals Accomplish this by reading the NxOUT read only bit of the NCOxCON register Th...

Страница 275: ...NCY MODE PFM OUTPUT OPERATION DIAGRAM Rev 10 000029A 11 7 2013 00000h 04000h 08000h FC000h 00000h 04000h 08000h FC000h 00000h 04000h 08000h 4000h 4000h 4000h NCO_interrupt NCOx Output FDC Mode NCOx Ou...

Страница 276: ...x output signal is active high non inverted bit 3 1 Unimplemented Read as 0 bit 0 NxPFM NCOx Pulse Frequency Mode bit 1 NCOx operates in Pulse Frequency mode 0 NCOx operates in Fixed Duty Cycle mode R...

Страница 277: ...leared bit 7 0 NCOxACC 7 0 NCOx Accumulator Low Byte R W 0 0 R W 0 0 R W 0 0 R W 0 0 R W 0 0 R W 0 0 R W 0 0 R W 0 0 NCOxACC 15 8 bit 7 bit 0 Legend R Readable bit W Writable bit U Unimplemented bit r...

Страница 278: ...mented bit read as 0 u Bit is unchanged x Bit is unknown n n Value at POR and BOR Value at all other Resets 1 Bit is set 0 Bit is cleared bit 7 0 NCOxINC 15 8 NCOx Increment High Byte Note 1 Write the...

Страница 279: ...following clock sources to be selected Fosc system clock HFINTOSC 16 MHz only The clock sources are selected using the G1CS0 bit of the CWGxCON0 register Register 26 1 26 3 Selectable Input Sources T...

Страница 280: ..._async PWM1_out NCO1_out LC1_out PWM2_out PWM3_out PWM4_out GxIS FOSC HFINTOSC GxCS C1OUT_async C2OUT_async LC2_out CWG1FLT INT pin GxASDSFLT GxASDSC1 GxASDSC2 GxASDSCLC2 GxASE Data Bit WRITE GxARSEN...

Страница 281: ...of the input source signal This duration is from 0 to 64 counts of dead band Dead band is always counted off the edge on the input source signal A count of 0 zero indicates that no dead band is prese...

Страница 282: ...83 PIC16 L F1508 9 FIGURE 26 3 DEAD BAND OPERATION CWGxDBR 01H CWGxDBF 02H FIGURE 26 4 DEAD BAND OPERATION CWGxDBR 03H CWGxDBF 04H SOURCE SHORTER THAN DEAD BAND Input Source CWGxA CWGxB cwg_clock sour...

Страница 283: ...CWG into the shutdown state When auto restart is disabled the shutdown state will persist as long as the GxASE bit is set When auto restart is enabled the GxASE bit will clear automatically and resum...

Страница 284: ...enables for the outputs to be used 7 Set the GxEN bit 8 Clear TRIS control bits corresponding to CWGxA and CWGxB to be used to configure those pins as outputs 9 If auto restart is to be used set the...

Страница 285: ...AUTO RESTART ENABLED GxARSEN 1 GxASDLA 01 GxASDLB 01 Shutdown GxASE Cleared by Software Output Resumes No Shutdown CWG Input GxASE CWG1A Source Shutdown Source Shutdown Event Ceases Tri State No Pulse...

Страница 286: ...ared q Value depends on condition bit 7 GxEN CWGx Enable bit 1 Module is enabled 0 Module is disabled bit 6 GxOEB CWGxB Output Enable bit 1 CWGxB is available on appropriate I O pin 0 CWGxB is not ava...

Страница 287: ...of the setting of the GxPOLB bit 01 CWGxB pin is tri stated 00 CWGxB pin is driven to its inactive state after the selected dead band interval GxPOLB still will control the polarity of the output bit...

Страница 288: ...own event has occurred bit 6 GxARSEN Auto Restart Enable bit 1 Auto restart is enabled 0 Auto restart is disabled bit 5 4 Unimplemented Read as 0 bit 3 GxASDSC2 CWG Auto shutdown on Comparator C2 Enab...

Страница 289: ...mplementary Waveform Generator CWGx Rising Counts 11 1111 63 64 counts of dead band 11 1110 62 63 counts of dead band 00 0010 2 3 counts of dead band 00 0001 1 2 counts of dead band 00 0000 0 counts o...

Страница 290: ...1EN G1OEB G1OEA G1POLB G1POLA G1CS0 287 CWG1CON1 G1ASDLB 1 0 G1ASDLA 1 0 G1IS 1 0 288 CWG1CON2 G1ASE G1ARSEN G1ASDSC2 G1ASDSC1 G1ASDSFLT G1ASDSCLC2 289 CWG1DBF CWG1DBF 5 0 290 CWG1DBR CWG1DBR 5 0 290...

Страница 291: ...out high voltage When the LVP bit of Configuration Words is set to 1 the ICSP Low Voltage Programming Entry mode is enabled To disable the Low Voltage ICSP mode the LVP bit must be programmed to 0 Ent...

Страница 292: ...pendent on the specific application and may include devices such as resistors diodes or even jumpers See Figure 27 3 for more information FIGURE 27 3 TYPICAL CONNECTION FOR ICSP PROGRAMMING 1 3 5 6 4...

Страница 293: ...ves a nominal instruction execution rate of 1 MHz All instruction examples use the format 0xhh to represent a hexadecimal number where h signifies a hexadecimal digit 28 1 Read Modify Write Operations...

Страница 294: ...control operations 13 8 7 0 OPCODE k literal k 8 bit immediate value 13 11 10 0 OPCODE k literal k 11 bit immediate value General CALL and GOTO instructions only MOVLP instruction only 13 5 4 0 OPCOD...

Страница 295: ...ff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C DC Z C DC Z Z C Z C Z C Z Z Z Z Z Z Z Z C C C DC Z C DC Z Z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ INCFSZ f d...

Страница 296: ...evice Reset Go into Standby mode Load TRIS register with W 1 1 1 1 1 1 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 0000 0010 0001 0011 0fff TO PD TO PD C COMPILE...

Страница 297: ...ter f ADDWFC ADD W and CARRY bit to f Syntax label ADDWFC f d Operands 0 f 127 d 0 1 Operation W f C dest Status Affected C DC Z Description Add W the Carry flag and data mem ory location f If d is 0...

Страница 298: ...o the PC Since the PC will have incre mented to fetch the next instruction the new address will be PC 1 W This instruction is a 2 cycle instruc tion BSF Bit Set f Syntax label BSF f b Operands 0 f 127...

Страница 299: ...nds 0 f 127 Operation 00h f 1 Z Status Affected Z Description The contents of register f are cleared and the Z bit is set CLRW Clear W Syntax label CLRW Operands None Operation 00h W 1 Z Status Affect...

Страница 300: ...us Affected Z Description The contents of register f are incre mented If d is 0 the result is placed in the W register If d is 1 the result is placed back in register f INCFSZ Increment f Skip if 0 Sy...

Страница 301: ...7 1 dest 6 0 f 0 C Status Affected C Z Description The contents of register f are shifted one bit to the right through the Carry flag A 0 is shifted into the MSb If d is 0 the result is placed in W If...

Страница 302: ...ly accesses the register at the address specified by the FSRn FSRn is limited to the range 0000h FFFFh Incrementing decrementing it beyond these bounds will cause it to wrap around MOVLB Move literal...

Страница 303: ...ecrementing it Note The INDFn registers are not physical registers Any instruction that accesses an INDFn register actually accesses the register at the address specified by the FSRn FSRn is limited t...

Страница 304: ...1 Cycles 2 Example TABLE CALL TABLE W contains table offset value W now has table value ADDWF PC W offset RETLW k1 Begin table RETLW k2 RETLW kn End of table Before Instruction W 0x07 After Instructio...

Страница 305: ...SUBLW Subtract W from literal Syntax label SUBLW k Operands 0 k 255 Operation k W W Status Affected C DC Z Description The W register is subtracted 2 s com plement method from the 8 bit literal k The...

Страница 306: ...Status Affected None Description Move data from W register to TRIS register When f 5 TRISA is loaded When f 6 TRISB is loaded When f 7 TRISC is loaded XORLW Exclusive OR literal with W Syntax label X...

Страница 307: ...PIC16 L F1508 9 DS40001609E page 308 2011 2015 Microchip Technology Inc NOTES...

Страница 308: ...amp current IK VPIN 0 or VPIN VDD 20 mA Total power dissipation 2 800 mW Note 1 Maximum current rating requires even load distribution across I O pins Maximum current rating may be limited by the devi...

Страница 309: ...g Temperature TA_MIN TA TA_MAX VDD Operating Supply Voltage 1 PIC16LF1508 9 VDDMIN Fosc 16 MHz 1 8V VDDMIN 16 MHz Fosc 20 MHz 2 5V VDDMAX 3 6V PIC16F1508 9 VDDMIN Fosc 16 MHz 2 3V VDDMIN 16 MHz Fosc 2...

Страница 310: ...013 5 5 2 5 2 3 0 16 20 V DD V Frequency MHz Note 1 The shaded region indicates the permissible combinations of voltage and frequency 2 Refer to Table 29 8 for each Oscillator mode s supported frequen...

Страница 311: ...Reset Release Voltage 2 1 6 V D002A 1 6 V D002B VPORR Power on Reset Rearm Voltage 2 0 8 V D002B 1 5 V D003 VFVR Fixed Voltage Reference Voltage 1x gain 1 024V nominal 2x gain 2 048V nominal 4x gain...

Страница 312: ...40001609E page 313 PIC16 L F1508 9 FIGURE 29 3 POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS VSS NPOR 1 TPOR 2 POR REARM Note 1 When NPOR is low the device is held in Reset 2 TPOR 1 s typi...

Страница 313: ...z External Clock ECM Medium Power mode 210 310 A 3 0 D014 180 270 A 2 3 FOSC 4 MHz External Clock ECM Medium Power mode 240 365 A 3 0 295 460 A 5 0 D015 3 2 12 A 1 8 FOSC 31 kHz LFINTOSC 40 C TA 85 C...

Страница 314: ...ons unless otherwise stated PIC16F1508 9 Param No Device Characteristics Min Typ Max Units Conditions VDD Note These parameters are characterized but not tested Data in Typ column is at 3 0V 25 C unle...

Страница 315: ...Operating Conditions unless otherwise stated PIC16F1508 9 Param No Device Characteristics Min Typ Max Units Conditions VDD Note These parameters are characterized but not tested Data in Typ column is...

Страница 316: ...WDT Current 0 44 3 0 10 A 3 0 D023 0 43 6 0 15 A 2 3 WDT Current 0 53 7 0 20 A 3 0 0 64 8 0 22 A 5 0 D023A 15 28 30 A 1 8 FVR Current 18 30 33 A 3 0 D023A 18 33 35 A 2 3 FVR Current 19 35 37 A 3 0 20...

Страница 317: ...9 38 40 A 5 0 TABLE 29 3 POWER DOWN CURRENTS IPD 1 2 CONTINUED PIC16LF1508 9 Operating Conditions unless otherwise stated Low Power Sleep Mode PIC16F1508 9 Low Power Sleep Mode VREGPM 1 Param No Devic...

Страница 318: ...in at high impedance 125 C D061 MCLR 3 50 200 nA VSS VPIN VDD Pin at high impedance 85 C IPUR Weak Pull up Current D070 25 100 200 A VDD 3 3V VPIN VSS 25 140 300 A VDD 5 0V VPIN VSS VOL Output Low Vol...

Страница 319: ...yp column is at 3 0V 25 C unless otherwise stated These parameters are for design guidance only and are not tested Note 1 Self write and Block Erase 2 Required only if single supply programming is dis...

Страница 320: ...S 2 TppS T F Frequency T Time Lowercase letters pp and their meanings pp cc CCP1 osc CLKIN ck CLKOUT rd RD cs CS rw RD or WR di SDIx sc SCKx do SDO ss SS dt Data in t0 T0CKI io I O PORT t1 T1CKI mc MC...

Страница 321: ...xternal CLKIN High External CLKIN Low 2 s LP Oscillator 100 ns XT Oscillator 20 ns HS Oscillator OS05 TosR TosF External CLKIN Rise External CLKIN Fall 0 ns LP Oscillator 0 ns XT Oscillator 0 ns HS Os...

Страница 322: ...e stated These parameters are for design guidance only and are not tested Note 1 To ensure these oscillator frequency tolerances VDD and VSS must be capacitively decoupled as close to the device as po...

Страница 323: ...H2ioI Fosc Q2 cycle to Port input invalid I O in setup time 50 ns 3 3V VDD 5 0V OS17 TioV2osH Port input valid to Fosc Q2 cycle I O in setup time 20 ns OS18 TioR Port output rise time 40 15 72 32 ns V...

Страница 324: ...age 325 PIC16 L F1508 9 FIGURE 29 8 RESET WATCHDOG TIMER OSCILLATOR START UP TIMER AND POWER UP TIMER TIMING VDD MCLR Internal POR PWRT Time out OSC Start up Time Internal Reset 1 Watchdog Timer 33 32...

Страница 325: ...n out Reset Voltage 2 2 55 2 35 1 80 2 70 2 45 1 90 2 85 2 58 2 05 V V V BORV 0 BORV 1 PIC16LF1508 9 BORV 1 PIC16LF1508 9 36 VHYST Brown out Reset Hysteresis 0 25 75 mV 40 C TA 85 C 37 TBORDC Brown ou...

Страница 326: ...me Synchronous No Prescaler 0 5 TCY 20 ns Synchronous with Prescaler 15 ns Asynchronous 30 ns 46 TT1L T1CKI Low Time Synchronous No Prescaler 0 5 TCY 20 ns Synchronous with Prescaler 15 ns Asynchronou...

Страница 327: ...e Rise Time OS18 Note 1 Fall Time OS19 Note 1 CLC04 FCLCMAX CLC maximum switching frequency 45 MHz These parameters are characterized but not tested Data in Typ column is at 3 0V 25 C unless otherwise...

Страница 328: ...ge 1 8 VDD V VREF VRPOS VRNEG Note 4 AD07 VAIN Full Scale Range VSS VREF V AD08 ZAIN Recommended Impedance of Analog Voltage Source 10 k Can go higher if external 0 01 F capacitor is present on input...

Страница 329: ...C_clk ADC Data ADRES ADIF GO Sample OLD_DATA Sampling Stopped DONE NEW_DATA 9 8 7 3 2 1 0 1 TCY 6 AD133 1 TCY AD132 AD132 AD131 AD130 BSF ADCON0 GO Q4 ADC_clk ADC Data ADRES ADIF GO Sample OLD_DATA Sa...

Страница 330: ...eters are for design guidance only and are not tested Note 1 The ADRES register may be read on the following TCY cycle Operating Conditions unless otherwise stated VDD 3 0V TA 25 C Param No Sym Charac...

Страница 331: ...ese parameters are characterized but not tested Note 1 See Section 30 0 DC and AC Characteristics Graphs and Charts for operating characterization 2 Settling time measured while DACR 4 0 transitions f...

Страница 332: ...8 USART SYNCHRONOUS RECEIVE REQUIREMENTS Standard Operating Conditions unless otherwise stated Param No Symbol Characteristic Min Max Units Conditions US125 TDTV2CKL SYNC RCV Master and Slave Data hol...

Страница 333: ...G CKE 1 SMP 1 SS SCK CKP 0 SCK CKP 1 SDO SDI SP81 SP71 SP72 SP73 SP74 SP75 SP76 SP78 SP79 SP80 SP79 SP78 MSb LSb bit 6 1 MSb In LSb In bit 6 1 Note Refer to Figure 29 4 for load conditions SS SCK CKP...

Страница 334: ...1 SS SCK CKP 0 SCK CKP 1 SDO SDI SP70 SP71 SP72 SP73 SP74 SP75 SP76 SP77 SP78 SP79 SP80 SP79 SP78 MSb LSb bit 6 1 MSb In bit 6 1 LSb In SP83 Note Refer to Figure 29 4 for load conditions SS SCK CKP 0...

Страница 335: ...rise time 10 25 ns 3 0V VDD 5 5V 25 50 ns 1 8V VDD 5 5V SP76 TDOF SDO data output fall time 10 25 ns SP77 TSSH2DOZ SS to SDO output high impedance 10 50 ns SP78 TSCR SCK output rise time Master mode...

Страница 336: ...ion Setup time 400 kHz mode 600 SP91 THD STA Start condition 100 kHz mode 4000 ns After this period the first clock pulse is generated Hold time 400 kHz mode 600 SP92 TSU STO Stop condition 100 kHz mo...

Страница 337: ...0 9 s SP107 TSU DAT Data input setup time 100 kHz mode 250 ns Note 2 400 kHz mode 100 ns SP109 TAA Output valid from clock 100 kHz mode 3500 ns Note 1 400 kHz mode ns SP110 TBUF Bus free time 100 kHz...

Страница 338: ...specified range Typical represents the mean of the distribution at 25 C MAXIMUM Max MINIMUM or Min represents mean 3 or mean 3 respectively where is a standard deviation over each temperature range N...

Страница 339: ...kHz PIC16LF1508 9 ONLY FIGURE 30 2 IDD LP OSCILLATOR FOSC 32 kHz PIC16F1508 9 ONLY Typical Max 0 2 4 6 8 10 12 14 16 18 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD A VDD V Max 85 C 3 Typical...

Страница 340: ...4 IDD MAXIMUM XT AND EXTRC OSCILLATOR PIC16LF1508 9 ONLY 4 MHz EXTRC 4 MHz XT 1 MHz EXTRC 1 MHz XT 0 50 100 150 200 250 300 350 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD A VDD V Typical 25...

Страница 341: ...RE 30 6 IDD MAXIMUM XT AND EXTRC OSCILLATOR PIC16F1508 9 ONLY 4 MHz EXTRC 4 MHz XT 1 MHz EXTRC 1 MHz XT 0 50 100 150 200 250 300 350 400 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 I DD A VDD V Typical 25 C 4...

Страница 342: ...SC 32 kHz PIC16LF1508 9 ONLY FIGURE 30 8 IDD EXTERNAL CLOCK ECL LOW POWER MODE FOSC 32 kHz PIC16F1508 9 ONLY Typical Max 0 2 4 6 8 10 12 14 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD A VDD V...

Страница 343: ...PIC16LF1508 9 ONLY FIGURE 30 10 IDD EXTERNAL CLOCK ECL LOW POWER MODE FOSC 500 kHz PIC16F1508 9 ONLY Max Typical 0 5 10 15 20 25 30 35 40 45 50 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD A...

Страница 344: ...MODE PIC16LF1508 9 ONLY FIGURE 30 12 IDD MAXIMUM EXTERNAL CLOCK ECM MEDIUM POWER MODE PIC16LF1508 9 ONLY 4 MHz 1 MHz 0 50 100 150 200 250 300 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD A VD...

Страница 345: ...UM POWER MODE PIC16F1508 9 ONLY FIGURE 30 14 IDD MAXIMUM EXTERNAL CLOCK ECM MEDIUM POWER MODE PIC16F1508 9 ONLY 4 MHz 1 MHz 0 50 100 150 200 250 300 350 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 I DD A VDD...

Страница 346: ...8 9 ONLY FIGURE 30 16 IDD MAXIMUM EXTERNAL CLOCK ECH HIGH POWER MODE PIC16LF1508 9 ONLY 20 MHz 16 MHz 8 MHz 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD mA VDD...

Страница 347: ...E PIC16F1508 9 ONLY FIGURE 30 18 IDD MAXIMUM EXTERNAL CLOCK ECH HIGH POWER MODE PIC16F1508 9 ONLY 20 MHz 16 MHz 8 MHz 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 I DD mA VDD V...

Страница 348: ...OSC 31 kHz PIC16LF1508 9 ONLY FIGURE 30 20 IDD LFINTOSC FOSC 31 kHz PIC16F1508 9 ONLY Typical Max 0 2 4 6 8 10 12 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD A VDD V Max 85 C 3 Typical 25 C T...

Страница 349: ...508 9 ONLY FIGURE 30 22 IDD MFINTOSC FOSC 500 kHz PIC16F1508 9 ONLY Typical Max 0 50 100 150 200 250 300 350 400 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD A VDD V Max 85 C 3 Typical 25 C Ty...

Страница 350: ...08 9 ONLY FIGURE 30 24 IDD MAXIMUM HFINTOSC PIC16LF1508 9 ONLY 16 MHz 8 MHz 4 MHz 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD mA VDD V Typical 25 C 16 MHz 8 MH...

Страница 351: ...INTOSC PIC16F1508 9 ONLY FIGURE 30 26 IDD MAXIMUM HFINTOSC PIC16F1508 9 ONLY 16 MHz 8 MHz 4 MHz 0 0 0 2 0 4 0 6 0 8 1 0 1 2 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 I DD mA VDD V Typical 25 C 16 MHz 8 MHz...

Страница 352: ...ONLY FIGURE 30 28 IDD MAXIMUM HS OSCILLATOR PIC16LF1508 9 ONLY 20 MHz 8 MHz 4 MHz 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I DD mA VDD V Typical 25 C 20 MHz...

Страница 353: ...ATOR PIC16F1508 9 ONLY FIGURE 30 30 IDD MAXIMUM HS OSCILLATOR PIC16F1508 9 ONLY 20 MHz 8 MHz 4 MHz 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 8 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 I DD mA VDD V Typical 25...

Страница 354: ...16F1508 9 ONLY 450 M 85 C 3 Max 250 300 350 400 450 D nA Max 85 C 3 Typical 25 C Typical 0 50 100 150 200 250 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I PD nA 0 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0...

Страница 355: ...8 1 0 1 2 1 4 1 6 1 8 2 0 I PD A Max 85 C 3 Typical 25 C Typical 0 0 0 2 0 4 0 6 0 8 1 0 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I PD A 0 0 0 2 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8...

Страница 356: ...E FVR PIC16F1508 9 ONLY 45 Max 85 C 3 Typical Max 20 25 30 35 40 45 I PD A Max 85 C 3 Typical 25 C 0 5 10 15 20 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I PD A 0 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0...

Страница 357: ...C16LF1508 9 ONLY Max 10 Typical Max 4 5 6 7 8 9 10 D A Max 85 C 3 Typical 25 C 0 1 2 3 4 5 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I PD A 0 1 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 VD...

Страница 358: ...OWN OUT RESET BOR BORV 1 PIC16F1508 9 ONLY M 12 Typical Max 6 8 10 12 I PD A Max 85 C 3 Typical 25 C 0 2 4 6 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 I PD A 0 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 VDD V Max...

Страница 359: ...8 9 ONLY 8 0 Max 85 C 3 Max 3 0 4 0 5 0 6 0 7 0 8 0 I PD A Max 85 C 3 Typical 25 C Typical 0 0 1 0 2 0 3 0 4 0 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I PD A 0 0 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3...

Страница 360: ...OWER MODE CxSP 0 PIC16F1508 9 ONLY 14 Typical Max 6 8 10 12 14 I PD A Typical 0 2 4 6 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I PD Max 85 C 3 Typical 25 C 0 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2...

Страница 361: ...1 PIC16F1508 9 ONLY 40 Typical Max 15 20 25 30 35 40 I PD A Typical 0 5 10 15 20 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 I PD A Max 85 C 3 Typical 25 C 0 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3...

Страница 362: ...508 9 ONLY FIGURE 30 48 VOL vs IOL OVER TEMPERATURE VDD 5 5V PIC16F1508 9 ONLY Min 40 C Typical 25 C Max 125 C 0 1 2 3 4 5 6 45 40 35 30 25 20 15 10 5 0 V OH V IOH mA Max 125 C 3 Typical 25 C Min 40 C...

Страница 363: ...V FIGURE 30 50 VOL vs IOL OVER TEMPERATURE VDD 3 0V Min 40 C Typical 25 C Max 125 C 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 15 13 11 9 7 5 3 1 V OH V IOH mA Max 125 C 3 Typical 25 C Min 40 C 3 Min 40 C Typica...

Страница 364: ...IOL OVER TEMPERATURE VDD 1 8V PIC16LF1508 9 ONLY Min 40 C Typical 25 C Max 125 C 0 0 0 2 0 4 0 6 0 8 1 0 1 2 1 4 1 6 1 8 2 0 4 5 4 0 3 5 3 0 2 5 2 0 1 5 1 0 0 5 0 0 V OH V IOH mA Max 125 C 3 Typical...

Страница 365: ...ONLY Typical Max Min 1 50 1 52 1 54 1 56 1 58 1 60 1 62 1 64 1 66 1 68 1 70 60 40 20 0 20 40 60 80 100 120 140 Voltage V Temperature C Max Typical 3 Typical 25 C Min Typical 3 Typical Max Min 1 34 1...

Страница 366: ...LY FIGURE 30 56 BROWN OUT RESET HYSTERESIS BORV 1 PIC16LF1508 9 ONLY Typical Max Min 1 80 1 85 1 90 1 95 2 00 60 40 20 0 20 40 60 80 100 120 140 Voltage V Temperature C Max Typical 3 Min Typical 3 Typ...

Страница 367: ...RE 30 58 BROWN OUT RESET HYSTERESIS BORV 1 PIC16F1508 9 ONLY Typical Max Min 2 30 2 35 2 40 2 45 2 50 2 55 2 60 60 40 20 0 20 40 60 80 100 120 140 Voltage V Temperature C Max Typical 3 Min Typical 3 T...

Страница 368: ...nology Inc DS40001609E page 369 PIC16 L F1508 9 FIGURE 30 59 BROWN OUT RESET VOLTAGE BORV 0 Typical Max Min 2 55 2 60 2 65 2 70 2 75 2 80 60 40 20 0 20 40 60 80 100 120 140 Voltage V Temperature C Max...

Страница 369: ...61 LOW POWER BROWN OUT RESET HYSTERESIS LPBOR 0 Typical Max Min 1 80 1 90 2 00 2 10 2 20 2 30 2 40 2 50 60 40 20 0 20 40 60 80 100 120 140 Voltage V Temperature C Max Typical 3 Min Typical 3 Typical...

Страница 370: ...in 10 12 14 16 18 20 22 24 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 Time ms VDD V Max Typical 3 40 C to 125 C Typical statistical mean 25 C Min Typical 3 40 C to 125 C Typical Max Min 40 50 60 70 80 90...

Страница 371: ...8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 Time us VDD V Max Typical 3 Typical statistical mean 25 C Note The FVR Stabilization Period applies when 1 coming out of RESET or exiting Sleep mode for PIC1...

Страница 372: ...FIGURE 30 66 COMPARATOR HYSTERESIS LOW POWER MODE CxSP 0 CxHYS 1 Min Typical Max 0 5 10 15 20 25 30 35 40 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 Hysteresis mV VDD V Max Typical 3 Typical 25 C Min Typ...

Страница 373: ...8 COMPARATOR RESPONSE TIME OVER TEMPERATURE NORMAL POWER MODE CxSP 1 Max Typical 0 50 100 150 200 250 300 350 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 Time ns VDD V Max Typical 3 Typical 25 C Min 40 C...

Страница 374: ...PIC16 L F1508 9 FIGURE 30 69 COMPARATOR INPUT OFFSET AT 25 C NORMAL POWER MODE CxSP 1 PIC16F1508 9 ONLY Max Typical Min 50 40 30 20 10 0 10 20 30 40 50 0 0 1 0 2 0 3 0 4 0 5 0 Offset Voltage mV Common...

Страница 375: ...RE PIC16F1508 9 ONLY Typical Max Min 20 22 24 26 28 30 32 34 36 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3 6 3 8 Frequency kHz VDD V Max Typical 3 40 C to 125 C Typical statistical mean 25 C Min Typica...

Страница 376: ...RE 30 73 HFINTOSC ACCURACY OVER TEMPERATURE 2 3V VDD 5 5V Typical Max Min 10 8 6 4 2 0 2 4 6 8 60 40 20 0 20 40 60 80 100 120 140 Accuracy Temperature C Max Typical 3 Typical statistical mean Min Typi...

Страница 377: ...5 Microchip Technology Inc FIGURE 30 74 SLEEP MODE WAKE PERIOD WITH HFINTOSC SOURCE PIC16LF1508 9 ONLY Typical Max 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 1 6 1 8 2 0 2 2 2 4 2 6 2 8 3 0 3 2 3 4 3...

Страница 378: ...SC SOURCE VREGPM 1 PIC16F1508 9 ONLY FIGURE 30 76 SLEEP MODE WAKE PERIOD WITH HFINTOSC SOURCE VREGPM 0 PIC16F1508 9 ONLY Typical Max 0 5 10 15 20 25 30 35 2 0 2 5 3 0 3 5 4 0 4 5 5 0 5 5 6 0 Time us V...

Страница 379: ...Beans IDE MPLAB X IDE is an entirely new IDE with a host of free software components and plug ins for high performance application development and debugging Moving between tools and upgrading from sof...

Страница 380: ...debugging The MPASM Assembler features include Integration into MPLAB X IDE projects User defined macros to streamline assembly code Conditional assembly for multipurpose source files Directives that...

Страница 381: ...d long up to three meters interconnection cables 31 8 MPLAB ICD 3 In Circuit Debugger System The MPLAB ICD 3 In Circuit Debugger System is Microchip s most cost effective high speed hardware debugger...

Страница 382: ...ts Microchip has a line of evaluation kits and demonstra tion software for analog filter design KEELOQ security ICs CAN IrDA PowerSmart battery management SEEVAL evaluation system Sigma Delta ADC flow...

Страница 383: ...r code last digit of calendar year YY Year code last 2 digits of calendar year WW Week code week of January 1 is week 01 NNN Alphanumeric traceability code Pb free JEDEC designator for Matte Tin Sn Th...

Страница 384: ...Inc DS40001609E page 385 PIC16 L F1508 9 Package Marking Information Continued 20 Lead SSOP 5 30 mm Example 20 Lead QFN 4x4x0 9 mm Example PIN 1 PIN 1 E SS 3 e 1120123 PIC16F1508 PIC16 F1508 E ML 120...

Страница 385: ...gy Inc 32 2 Package Details The following sections give the technical details of the packages HDG 3ODVWLF XDO Q LQH 3 PLO RG 3 3 1RWHV 0 1 2 1 3 4 5 4 1RWH 6 7 7 588 8 7 9 1 4 7 7 0 4 1 0 0 0 7 1 B B...

Страница 386: ...1 2015 Microchip Technology Inc DS40001609E page 387 PIC16 L F1508 9 Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packa...

Страница 387: ...6 L F1508 9 DS40001609E page 388 2011 2015 Microchip Technology Inc Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packag...

Страница 388: ...1 2015 Microchip Technology Inc DS40001609E page 389 PIC16 L F1508 9 Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packa...

Страница 389: ...age 390 2011 2015 Microchip Technology Inc HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 PP RG 6623 1RWHV 1 0 1 3 4 5 4 165 1RWH 6 7 7 588 8 7 9 1 1 D 4 7 7 D B 1 B B 7 1 0 D D 6 6 16 7 6 E E BE 0B L L1 A2 c e...

Страница 390: ...1 2015 Microchip Technology Inc DS40001609E page 391 PIC16 L F1508 9 Note For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packa...

Страница 391: ...5 Microchip Technology Inc HDG 3ODVWLF 4XDG ODW 1R HDG 3DFNDJH 0 PP RG 4 1 1RWHV 7 0 1 3 4 5 4 165 1RWH 6 7 7 588 8 7 9 1 1 4 B 7 0 16 1 4 1 1 D B 4 1 D B B 0 0 1 G D EXPOSED PAD E E2 2 1 N TOP VIEW N...

Страница 392: ...2011 2015 Microchip Technology Inc DS40001609E page 393 PIC16 L F1508 9 1RWH 6 7 7 588 8 7...

Страница 393: ...OM VIEW For the most current package drawings please see the Microchip Packaging Specification located at http www microchip com packaging Note NOTE 1 1 2 N 0 10 C A B 0 10 C A B 0 10 C 0 08 C A1 Micr...

Страница 394: ...Units Dimension Limits A1 A b D E2 D2 A3 e L E N 0 50 BSC 0 127 REF 2 60 2 60 0 30 0 20 0 45 0 00 0 25 4 00 BSC 0 40 2 70 2 70 0 50 0 02 4 00 BSC MILLIMETERS MIN NOM 20 2 80 2 80 0 50 0 30 0 55 0 05...

Страница 395: ...Optional Center Pad Length Contact Pitch Y2 X2 2 80 2 80 MILLIMETERS 0 50 BSC MIN E MAX 4 00 Contact Pad Length X20 Contact Pad Width X20 Y1 X1 0 80 0 30 BSC Basic Dimension Theoretically exact value...

Страница 396: ...initions of address Section 3 2 Added clarification of Buffer Gain Selection bits Section 13 2 Removed Preliminary status from Section 30 Updated Figures 15 1 29 9 Clarified information in Registers 7...

Страница 397: ...chip sales offices distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip s customer notification service helps keep customers current on Microchip products Subscriber...

Страница 398: ...SS SSOP Pattern QTP SQTP Code or Special Requirements blank otherwise Examples a PIC16LF1508T I SO Tape and Reel Industrial temperature SOIC package b PIC16F1509 I P Industrial temperature PDIP packag...

Страница 399: ...PIC16 L F1508 9 DS40001609E page 400 2011 2015 Microchip Technology Inc NOTES...

Страница 400: ...istered trademark of Microchip Technology Inc in other countries GestIC is a registered trademark of Microchip Technology Germany II GmbH Co KG a subsidiary of Microchip Technology Inc in other countr...

Страница 401: ...Tel 86 24 2334 2829 Fax 86 24 2334 2393 China Shenzhen Tel 86 755 8864 2200 Fax 86 755 8203 1760 China Wuhan Tel 86 27 5980 5300 Fax 86 27 5980 5118 China Xian Tel 86 29 8833 7252 Fax 86 29 8833 7256...

Страница 402: ...6F1509 E SS PIC16F1509T I ML PIC16F1509T I SO PIC16F1509T I SS PIC16LF1508 E ML PIC16LF1508 E P PIC16LF1508 E SO PIC16LF1508 E SS PIC16LF1508 I ML PIC16LF1508 I P PIC16LF1508 I SO PIC16LF1508T I ML PI...

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