Microchip Technology dsPIC30F6010, Техническое описание

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 2004 Microchip Technology Inc.
Advance Information
DS70119B-page 71
dsPIC30F6010
12.0 INPUT CAPTURE MODULE
This section describes the Input Capture module and
associated operational modes. The features provided
by this module are useful in applications requiring
Frequency (Period) and Pulse measurement.
Figure 12-1 depicts a block diagram of the Input
Capture module. Input capture is useful for such modes
as:
• Frequency/Period/Pulse Measurements
• Additional sources of External Interrupts
The key operational features of the Input Capture
module are:
• Simple Capture Event mode
• Timer2 and Timer3 mode selection
• Interrupt on input capture event
These operating modes are determined by setting the
appropriate bits in the ICxCON register (where x =
1,2,...,N). The dsPIC30F6010 device has 8 capture
channels.
FIGURE 12-1: INPUT CAPTURE MODE BLOCK DIAGRAM
12.1 Simple Capture Event Mode
The simple capture events in the dsPIC30F product
family are:
• Capture every falling edge
• Capture every rising edge
• Capture every 4th rising edge
• Capture every 16th rising edge
• Capture every rising and falling edge
These simple Input Capture modes are configured by
setting the appropriate bits ICM<2:0> (ICxCON<2:0>).
12.1.1 CAPTURE PRESCALER
There are four input capture prescaler settings, speci-
fied by bits ICM<2:0> (ICxCON<2:0>). Whenever the
capture channel is turned off, the prescaler counter will
be cleared. In addition, any Reset will clear the
prescaler counter.
12.1.2 CAPTURE BUFFER OPERATION
Each capture channel has an associated FIFO buffer,
which is four 16-bit words deep. There are two status
flags, which provide status on the FIFO buffer:
• ICBFNE - Input Capture Buffer Not Empty
• ICOV - Input Capture Overflow
The ICBFNE will be set on the first input capture event
and remain set until all capture events have been read
from the FIFO. As each word is read from the FIFO, the
remaining words are advanced by one position within
the buffer.
ICxBUF
Prescaler
ICx
ICM<2:0>
Mode Select
3
Note:
Where ‘x’ is shown, reference is made to the registers or bits associated to the respective input
capture channels 1 through N.
1 0
Set Flag
Pin
ICxIF
ICTMR
T2_CNT
T3_CNT
Edge
Detection
Logic
Clock
Synchronizer
1, 4, 16
From GP Timer Module
16 16
FIFO
R/W
Logic
ICI<1:0>
ICBNE, ICOV
ICxCON
Interrupt
Logic
Set Flag
ICxIF Data Bus