Microchip Technology dsPIC30F6010, Техническое описание

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dsPIC30F6010
DS70119B-page 130
Advance Information

2004 Microchip Technology Inc.
20.4 Programming the Start of
Conversion Trigger
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to 5 alternate sources of
conversion trigger.
When SSRC<2:0> =
000
, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> =
111
(Auto Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least 1 clock cycle.
Other trigger sources can come from timer modules,
Motor Control PWM module, or external interrupts.
20.5 Aborting a Conversion
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing. The ADCBUF will not be updated with the partially
completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an auto
start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T AD wait is
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the
next channel converted. If simultaneous sampling is
specified, the A/D will continue with the next
multi-channel group conversion sequence.
20.6 Selecting the A/D Conversion
Clock
The A/D conversion requires 13 T AD . The source of the
A/D conversion clock is software selected using a six
bit counter. There are 64 possible options for T
AD .
EQUATION 20-1: A/D CONVERSION CLOCK
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
AD
) must be selected to ensure a minimum T
AD
time
of 154 nsec. Table 20-1 shows the resultant T AD times
derived from the device operating frequencies and the
A/D clock source selected, (for V
DD
= 5V).
TABLE 20-1: TYPICAL T
AD
VS. DEVICE OPERATING FREQUENCIES
T
AD
= T
CY
* (0.5*(ADCS<5:0> +1))
A/D Clock Period (T
AD
Values)
A/D Clock Source Select Device F
CY
A/D
Clock
ADRC ADCS<5:0> 30 MHz 25 MHz 12.5 MHz 6.25 MHz 1 MHz
T
CY
/2 0
000000
16.67 ns
(2)
20 ns
(2)
40 ns
(2)
80 ns
(2)
500 ns
T
CY
0
000001
33.33 ns
(2)
40 ns
(2)
80 ns
(2)
160 ns 1.0
µ
s
2 T
CY
0
000011
66.66 ns
(2)
80 ns
(2)
160 ns 320 ns 2.0
µ
s
(3)
4 T
CY
0
000111
133.32 ns
(2)
160 ns 320 ns 640 ns
(3)
4.0
µ
s
(3)
8 T
CY
0
001111
266.64 ns 320 ns 640 ns
(3)
1.28
µ
s
(3)
8.0
µ
s
(3)
16 T
CY
0
011111
533.28 ns
(3)
640 ns
(3)
1.28
µ
s
(3)
2.56
µ
s
(3)
16.0
µ
s
(3)
32 T
CY
0 111111
1066.56 ns
(3)
1280 ns
(3)
2.56
µ
s
(3)
5.12
µ
s
(3)
32.0
µ
s
(3)
RC
1 xxxxxx
200-400 ns
(1,4)
200-400 ns
(1,4)
200-400 ns
(1,4)
200-400 ns
(1,4)
200-400 ns
(1)
Note 1: The RC source has a typical T
AD
time of 300 ns for V
DD
> 3.0V.
2: These values violate the minimum required T
AD
time of 154 ns.
3: For faster conversion times, the selection of another clock source is recommended.
4: A/D cannot meet full accuracy with RC clock source and F
OSC
> 20 MHz.